Packet Classification Apps Just Got a Whole Lot Easier to Manage: MoSys’s New Graph Memory Engine™ Running on Xilinx UltraScale+ with TCAM Compiler

Virtualized Acceleration: The MoSys Approach

Effectively utilizing and deploying hardware in multiuser environments has long been an issue in many systems. Virtualization allows for more flexibility in how many users can utilize hardware and how easily software applications can be moved from one platform to another and be configured.

32 Reasons to Love 32 RISC Cores

The MoSys PHE accelerator engine comes with 1Gb of memory and 32 RISC cores. Why you ask? We get that a lot. Not the 1Gb of memory but 32 RISC cores. Why would any applications need 32 cores?

That’s Another Wrap! XDF Europe 2019 is in the Books

Xilinx continues to provide leadership technology which enables groundbreaking products and services that we take for granted every day across an amazing array of markets.

What a Virtualized Accelerator Engine Can Do for Your Data

I have been thinking about data a lot recently and the power it now wields in our lives. To that end, I just read that the entire digital universe is expected to reach 44 zettabytes by 2020. If this estimate is anywhere close to being accurate, it will mean that there will be 40 times more bytes than stars we have counted in the observable universe.

Get Your Head in the Cloud with 100G Gearbox Solutions with the MoSys LineSpeed™ Flex PHY

Worldwide shipments and revenue for 100Gb Ethernet switches have been growing rapidly, reaching 3.8M ports and $1.1B revenue for Q4, 2018, according to IDC.

The Anatomy of Virtualized Accelerator Engine Technology

MoSys recently announced a family of Accelerator Engines which immediately prompted a series of questions. One of the most common comments was when people asked us to specifically define what an accelerator engine was.

XDF Post Show

That’s a Wrap! Essential Facts from XDF 2019

The Curious Case of Memory Bottleneck

With technology advances it is becoming more compelling to move the processor elements closer to or even into the memory without paying a cost penalty for replicating processing elements.