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  • Accelerator Engine Strategy
  • Products
    • QUAZAR FAMILY – Quad Partition Rate ICs
      • New…Quazar Quad Partition Rate Memories
    • BLAZAR FAMILY – Accelerator Engine ICs
      • Blazar Family Overview
      • PHE-Programmable HyperSpeed Engine Memory IC
      • BE3RMW – Bandwidth Engine 3 – RMW
      • BE3BURST-Bandwidth Engine 3 – BURST
      • BE2RMW-Bandwidth Engine 2-RMW
      • BE2BURST – Bandwidth Engine 2 – BURST
      • RTL Memory Controller BE2-3 Product Brief
    • STELLAR FAMILY – Virtual Accelerator Engines
      • Stellar Virtual Accelerator Engine Overview
      • Stellar Packet Classification Platform
    • LINESPEED FAMILY
      • LineSpeed Family Overview
      • 100G Octal Retimer with RS-FEC
      • 100G Full-Duplex Retimer with RS-FEC
      • 10 Lane Full Duplex 25G Retimer with FEC
      • 100G Gearbox with RS-FEC
      • 100G Multi-Link Gearbox (MLG) for Modules
      • 100G Multi-Link Gearbox (MLG) for Line Cards
      • Multi-Channel 2:1 Serial Mux/Demux
    • DEVELOPMENT KITS
      • Cheetah Dev Kit
      • Support Tools – BE2 Compact FMC Dev Kit
      • Support Tools – BE2 Dual FMC Dev Kit
      • Support Tools – BE2 Extended FMC Dev Kit
      • Support Tools – BE3 Dual FMC Dev Kit
      • Support Tools – IC Spotlight Analyzer
  • Use Cases
    • VIRTUAL ACCELERATOR ENGINES
      • Packet Classification for Anti-Distributed Denial of Service (DDoS) Engines – Combining AI/ML with ACL Lookups
      • Packet Classification for Next Generation Network Firewalls
    • LINESPEED
      • Redundant Link Mode for High-Rel Data Transfer
      • Multiplexing and Demultiplexing High-Speed Serial Links
    • ACCELERATOR ENGINES
      • FPGA Acceleration
      • FPGA Reference Designs
      • Metro Ethernet
      • Edge Router
      • Data Center Security
      • Routers
      • Video
      • Data Center SDN Switch
  • Technology
    • QUAD PARTITION RATE MEMORY TECHNOLOGY
      • Quazar QPR (Quad Partition Rate) Architecture
      • Quazar FPGA RTL Memory Quazar QPR Controller Selector
    • ACCELERATOR ENGINE TECHNOLOGY
      • Accelerator Engine (AE) Devices
      • AE Block Diagrams
      • Memory Configuration
      • AE vs QDR
      • Serial vs Parallel Memories
      • MoSys FPGA RTL Controller
      • Advanced Accelerator In-Memory Function
        • In-Memory BURST
        • In-Memory RMW
        • In-Memory User Programmable
      • Advanced Application Use
        • 32 RISC Core Architecture
      • STD Memory Use
      • Advanced Device Uses
        • Dual Port / Pipeline
        • Super High Bandwidth
    • VIRTUAL ACCELERATOR TECHNOLOGY
      • Stellar Virtual Acceleration Technology
      • Stellar Packet Classification Platform
    • OTHER
      • In Memory Functions – Fixed Functions (BURST/RMW)
      • PHE – RISC Core Instruction Set
      • GigaChip Interface (IP)
  • Blog
  • Design Support
    • KNOWLEDGE BASE
      • Newsletters
      • Solution Notes
      • Application Notes
      • Design Guidelines & Selector Guidelines
    • VIDEOS & WEBINARS
      • Product and General Videos
      • Webinars
        • Virtualized Acceleration: The Mosys Approach
    • SUPPORT DOCUMENTS
      • White Papers
        • Quazar QPR (Quad Partition Rate) Architecture
        • Stellar Virtual Accelerator Engines
        • Chiplet Interconnect – Parallel or Serial?
      • Tech Briefs
        • MoSys FPGA RTL Memory Controller Selector
    • SUPPORT TOOLS
      • Cheetah Dev Kit
      • BE2 Compact FMC Dev Kit
      • BE2 Dual FMC Dev Kit
      • BE2 Extended FMC Dev Kit
      • BE3 Dual FMC Dev Kit
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HomeBlog

Future Proofing Your Next Design

February 17, 2021

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Increasing 40Gb Ethernet Link Density with the MoSys LineSpeed™ Flex Mux/Demux PHY Device

February 11, 2021

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Kick Off 2021 with MoSys

January 12, 2021

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Forward Looking from MoSys in 2021

January 5, 2021

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2020: What a Year It’s Been

December 29, 2020

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Finish 2020 Strong with MoSys!

December 22, 2020

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Why Have ALUs on a Memory Die?

December 16, 2020

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Packet Classification for Anti-Distributed Denial of Service (DDoS) Engines – Combining AI/ML with ACL Lookups

December 9, 2020

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Use Case: Redundant Link Mode

November 30, 2020

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Featured Posts

  • Future Proofing Your Next Design
    February 17, 2021
  • Increasing 40Gb Ethernet Link Density with the MoSys LineSpeed™ Flex Mux/Demux PHY Device
    February 11, 2021
  • Kick Off 2021 with MoSys
    January 12, 2021
  • Forward Looking from MoSys in 2021
    January 5, 2021

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MoSys’ innovative Memory ICs improve system speed and performance while eliminating data throughput and access bottlenecks on line cards and systems with aggregate rates above 100Gbps.

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