MoSys had defined three groups of Embedded In-Memory Functions (EIMFs):

  • Fixed BURST functions
  • Fixed RMW Functions
  • Programmable Functions

Each group delivers different increments of performance acceleration. Which EIMF group of functions are embedded defines a particular MoSys Accelerator Engine. 

  Embedded In-Memory Functions (EIMFs)
DensityBURST Group for speedRMW Group for computingProgrammable Group for Algorithms
HyperSpeed Engine1.152GbXXX
Bandwidth Engine 3 - RMW1.152GbXX
Bandwidth Engine 2 - RMW576MbXX
Bandwidth Engine 3 - BURST1.152GbX
Bandwidth Engine 2 - BURST576MbX

There Are Five Key Attributes That Differentiate Accelerator Engine Memory ICs

Advanced, Multi-Level SRAM Memory Architecture

The primary memory for the entire BLAZAR family is our fast, accurate and efficient partitioned SRAM memory. These memories deliver a core cycle time (tRC) of 2.67ns and can perfom up to 6 billion simultaneous READS and WRITES with a latency of less than 13ns.

High-Speed SerDes I/O

Our GigaChip Interface technology enables serial data to be transmitted up to 28Gbps to and from an FPGA or processor. With 16 serial lanes, this is done with as few as 8 pins in some cases. 

Embedded In-Memory Functions (EIMFs)

All members of the BLAZAR family have some form of EIMFs to accelerate performance. Our BURST products (BE2-BURST and BE3-BURST) use these functions to move data more efficiently and is ideal for high-bandwidth applications.

Our RMW products (BE2-RMW and BE3-RMW) add additional functions that are common and repetitive in some applications. This means that data can be processed and modified directly in the memory without having to be passed all the way back to the FPGA.

The PHE (Programmable HyperSpeed Engine) also has the BURST and fixed RMW functions, but kicks it up a notch enabling designers to include their own algorithms to be performed within the memory. In other words, you can fine tune the memory to meet your specific needs.

Multi-Port Access

Multi-port access enables simultaneous operations to be executed in different sections of the memory.