Expanding High-Speed FPGA Memory

With the ever-increasing speed at which networks are running and the need for instantaneous access to data, it seems that there can never be enough memory. In most FPGA devices, the amount of high-speed SRAM like memory is now in the 300 to 400Mb range. This is rarely adequate for buffering, tables, statistics, etc. The predominant approach by the FPGA vendors has been to attach significant resources of High Bandwidth (HBM). Although this addresses some memory issues very well, it struggles to support high-speed, random access requirements.

To date, the approach has been to use QDR SRAM which provides high-speed memory access to an FPGA through a bus that is 100+ pins wide. Many  customers are hitting limitations with the use of QDR. They need more high-speed, random access memory and the QDR is too shallow, uses too many pins, and is difficult to expand.

MoSys customers have substantially expanded their on-chip FPGA SRAM by replacing a single or multiple QDR devices with a single MoSys QPR (Quad Partition Rate) device or by adding MoSys QPR devices onto boards that had no high-speed external memory. The MoSys QPR devices offer 2 to 4x the on-chip FPGA memory density and 4-8x the attached QDR external memory capacity in a single chip. In both scenarios, using a MoSys device with a serial interface, saved them design time (both at the PCB level and the FPGA – RTL level), board space, routing complexity, general purpose IOs and in some cases, also reduced PCB layer count (reducing cost).

The unique interface of the MoSys Device (Giga Chip Interface – GCI) also allows for easy depth expansion of the external memory resource. By utilizing the same 16 SerDes lanes, the interface has allowed customers the ability to offer different performance and throughput SKUs of a single PCB by loading different numbers of MoSys devices on a card.