Fixed Function IMFs for Speed (BURST)

BURST functions improve the efficiency of data transfers by reducing the number of data commands. In normal operation, every packet of data also has a command, either a request to READ or a request to WRITE. So if two items are transmitted and written to memory only one of them is the actual data you wanted to get there. BURST functions simply bundle multiple packets of data to a single command. If eight data packets would normally also have 8 commands, then it took 16 items of throughput. If you can bundle 8 to a single command then you can move 16 packets of data with just 3 commands. 

Using BURST functions, you can nearly double the amount of data going in-and-out of memory utilizing the same amount of bandwidth. After all, what’s the point of having high-bandwidth capability if half the data transferred doesn’t help your application perform functions. 

BURST Function Opcodes for BE2, BE3 and HyperSpeed Engines 

Throughput Benefits of BURST functions for BE2

SerDes Speed Grade
10.3125Gbps12.5Gbps
WidthBURSTThroughput (Gbps)Throughput (Gbps)
16 LanesBL8132160
BL4118.8144
BL299120
8 LanesBL86680
BL459.472
BL249.560
4 LanesBL83340
BL429.736
BL224.830

Throughput Benefits of BURST functions for BE3

SerDes Speed Grade
10.3125Gbps*12.5Gbps
WidthBURSTThroughput (Gbps)Throughput (Gbps)
16 LanesBL8132160
BL4118144
BL299120
8 LanesBL86680
BL459.472
BL249.560
4 LanesBL83340
BL429.736
BL224.830

RMW Fixed Function Opcodes for BE2, BE3 and Hyperspeed Engine

User Programmable Functions – RISC Core Instruction Set

  • ALU/logical functions on 72b
    • add, sub, adc,sbb, s1add, s2add, s3add, s3sub, and, or, xo, andn, sar, slr, sll, minu, maxu, mult
  • Bit field of variable len @varable pos
    • extract, deposit, chomp
    • can be across register boundaries
    • optional auto increase of pos
  • Test and branch functions
    • tsteq, tstgt,tstnle, tstlt, tstnge, tstgtu, tstnleu, tstltu, tstngeu, tstbs, tstne, tstle, tstngt, tstge, tstnlt, tstleu, tstngtu, tstgeu, tstnltu, tstbc
    • jmp, jeq, jgt, jnle, jlt, jnge, jgtu, jnleu, jltu, jngeu, jbs, jne, jle, jngt, jge, jnlt, jleu, jngtu, jgeu, jnltu, jbc
    • multiway branch 2, 3, 4
  • Loads and stores
    • local Dmem
      • 8b, 16b, 32b, 64b, 72b
      • reg + offset with auto incr reg
    • Partition
      • burst reads, load balanced reads and broadcast
      • 64b, 72b, 128b, 135b, 144b
      • reg + reg (or) reg + offset with auto incr reg
  • Atomic operations
    • Local
      • 8b, 16b, 32b, 64b
      • adda, suba, anda, xora, andna, xchga, cmpxchga
    • Partition
      • 16b, 32b, 64b
      • add(s), sub(s), xor, rd/set, tst/set, cmp/set, avg, tm, age
  • Program control
    • hlt, brk (and) nop
    • add/mov (and) halt (tread)
    • yield
  • Special registers
    • GPR indirect specification
    • auto increment
    • command, memory, result, result len
    • time stamp, random, zero, all ones, thread id, wake up, sink
  • Special functions
    • find first zero, find first one
    • population count
    • swap bits in bytes and bytes in words
    • 144b HASH to 72b (non crypto)
    • compute CRC32
    • multi-way compare with 4, 6, 9, (and) 12 inputs

Quick Links

PHE-Programmable HyperSpeed Engine Memory IC

The PHE features four levels of memory, 32 Risc core processors to perform user-programmed In-Memory Functions (IMFs), along with all of the fixed BURST and RMW functions included in the BE3 products. We combine this with our high-speed serial protocol I/O interface to enable your applications to achieve hyperspeed performance.

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