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Welcome to MoSys Solution Notes!

MoSys CTO, Michael Miller, will discuss insights into applications that he is interested in as well as applications that demonstrate how the MoSys Accelerator Engines can significantly improve FPGA design performance and simplify designs by giving software and hardware architects performance options not available before.

MoSys, a long time memory company, has used its application experience to design an Accelerator Engine that serially attaches to an FPGA and whose unique memory architectures, embedded memory functions for “Bandwidth” and “In Memory Computing”, a high speed-low pins count serial interface device actually defines a new memory space.

Add to the mix, 32 high performance RISC cores, and you have the ability to achieve what we call HyperSpeed performance with user defined embedded software.

Michael Miller, CTO … Has been with MoSys for 10 years. Prior, he was CTO and Systems Architecture at IDT. He has over 46 patents and holds the basic JTAG patent. See Michael’s biography on the MoSys Leadership page, under the About Us tab.

So, enjoy the technical exchange! We are always open to your suggestions for new topics.

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APPLICABLE DEVICESMEM SIZESerDes SPEEDALUIN MEMORY FUNCTIONS
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DOCBE2
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RMW
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PHE512MB1GB10G/12G25GBURSTRMWUser
Defined
Data
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32
Cores
1001Buffering up to 800 Gbps throughput with Bandwidth Engine Memory
Achieving 200 to 800 Gbps of buffered throughput can be a challenging task. Using serial attach BE devices can make that task more straight forward.

SOON

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1002Achieving 6.5 Billion Transactions/Sec in a Single Memory Device
Emerging applications are demanding more random transactions than ever before. Many now need to access a large address space at 2B random transactions per second or more. To keep up with demand, there are many more emerging applications that will exceed the random-access rates of memories such as QDR IV, SigmaQuad IVe, RLDRAM, DDR and HBM.

SOON

PDF

COMING SOON

  • FPGA Acceleration with -1Gb- tRC3ns… with 64 pins
    What is an FPGA Accelerator Engine?
  • Achieve 2.5 times the QDR access rate with a Serial Memory
    Serial, less signal pins, easier to design …at still achieve 2.5 higher Bandwidth.
  • Who is keeping count? Intelligent FPGA memories with In Memory Computing.
    Statistics? Stale counting data? An “In Memory Compute Function” of intellegent RMW solves these issues.
  • Is HBM overkill?
    A memory alternative when QDR takes up too much board space, and adding another HBM is your only Solution. How data is stored and used should detemine the size and type of the memory to need for today and future needs.
  • FPGA parallel memories vs serial – 1000s of signals or 64 ?
    Reduce FPGA board routing, timing, design time and complexity with Serial Memory.
  • Are Dual Port Memories Dead?
    They are not dead, just hard to design at the high speed requirements to todays application. New “Scale Out Architectures will welcome multiport memeries.
  • Power of 32!
    What could you do with 32 RISC cores with instruction and data memory on one chip?

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