MoSys Packet Classification
- Family of implementations ranges from:
- Pure software version (for maximum flexibility and capacity)
- FPGA versions (for up to 10x the performance of software alone)
- FPGA plus a MoSys Accelerator Engine (BE-2, BE-3 or PHE for up to 100X the performance of Software alone)
GME (Graph Memory Engine)
- The MoSys GME is proven compatible with Xilinx Ultrascale+ FPGAs and utilizes a common RTL interface to facilitate platform portability.
- This is the first of the MoSys Accelerator Platforms available as software through Hardware accelerated with a PHE and supports
- Xilinx, such as UltraScale+
MoSys’ Packet Classification Platform leverages the company’s innovative virtual accelerator, the Graph Memory Engine (GME), for performing embedded search and classification of packet headers as an alternative to TCAM functions. The platform includes software that compiles TCAM images into graphs for GME to process all versions are using a common API for portability.
As markets continue to migrate to software-defined environments, most notably software-defined networks (SDN), performance scaling has become key to remaining competitive while addressing the growing demands being placed on the network. Software investments now must be transferrable across multiple hardware environments in order to be both cost-effective and to provide the required flexibility to meet changing performance demands.
The MoSys Function Acceleration Platform is hardware agnostic and operates with or without a MoSys IC. For example, on a CPU or FPGA not attached to a MoSys IC, or an FPGA attached to a member of the MoSys Accelerator Engine IC family like the Bandwidth Engine or Programmable HyperSpeed Engine with in-memory compute capability. MoSys expects acceleration performance scaling across these platforms to be as high as 100x over standalone CPU implementations with an FPGA connected to a MoSys PHE. MoSys scalable solutions can meet today’s application needs, as well as provide a path that is flexible enough to adapt to new products and address new and more performance-driven market demands.
Silicon MoSys Accelerator Engines Support:
- BE2 Bandwidth Engine
- BE3 Bandwidth Engine
- PHE Programable HyperSpeed Engine
Silicon FPGA Families Support:
Currently the GME is supported on the Xilinx Ultrascale+ family of FPGAs. It is designed with the flexibility to support a range of performance goals and resource utilization to accommodate many different applications. Future families on the roadmap.
Hardware Support Options:
- Mosys Cheetah Dev Card
- PCIe based
- 2UI slots
- 8GB of DDR
- 2 QSOP interfaces
- FMC Card
- Available to support any Xilinx evaluation platform with FMC support
- Support for either BE-2, BE-3 or PHE
- MoSys PHE accelerator engine
- 1Gb of memory
- 32 RISC cores
- Acceleration cards
- 5G edge compute
- Security appliances
- Quality of Service based Traffic Switching
- Lawful Intercept
- NIC based OVS acceleration
- Software Defined Networking
- Aerospace and defense
- High-performance computing
- Data-driven applications
Target Embedded Functions:
- N-tuple search with wild card fields
- Regular Expression (RegEx, DFA)
- String Match using Patricia Tree
- Decision Tree
- Packet Parsing
The VAE can be adapted to any hardware environment for more information: Contact MoSys
At the core of providing a highly scalable platform is virtualizing the accelerator function by creating a functional abstraction with a high-level software API for a specific application area that can be implemented across different hardware and software environments. MoSys calls this a Virtual Accelerator Engine (VAE).
The VAE leverages a common application program interface (API) to enable a platform to achieve performance scaling of up to 100x. The same functions can scale from software running on a CPU; RTL running on an FPGA to very high-performance implementations which combine an FPGA connected to MoSys Accelerator Engine ICs with in-memory compute
Single Common API:
A Virtual Accelerator Engine (VAE) employs a common application program interface (API) to allow for platform solutions portability of a given accelerator function. Implementations can range from software on a CPU, to modules in FPGAs, to very high-end, highly accelerated solutions using FPGAs with MoSys Accelerator Engine ICs like the MoSys PHE with its 32 RISC cores and 1Gb of embedded memory.
Single Common RTL Interface
Most VAE platforms will have FPGA-based products with different performance capabilities. The RTL interface across these FPGA products will have a common RTL logic specification (VAE IF).
Designing to a common hardware interface allows for easy migration between different performance and capacity requirements. Additionally, the designer can create a wider range of product offerings and can more easily implement add-on acceleration modules. This provides future proofing because as new silicon becomes available with a VAE port, the designer can drop it into the same logical “socket”.
Performance Scalability Across Multiple Hardware Environments
Scalability comes from the ability of each implementation to take advantage of available compute and memory resources. Memory can range from DRAM adjacent to the CPU, to block memory or HBM on the FPGA or 1T-SRAM tightly coupled with 32 RISC engines in MoSys Accelerator Engine IC products.
The common API is presented to the common s/w (“C VAE IF) or across different FPGA configurations with the common RTL (VAE IF).
Adaption Layer Software to Higher Existing API
Implementation of a VAE will require an Adaptation Layer.
The adaptation layer provides a way for upper levels of software with an existing API to bridge to the VAE common API. The designer may develop their own adaption software libraries or choose to use software provided by MoSys as part of an application-specific platform.
If the user’s adaptation layer is included in every system, the application API would be common across different hardware environment, and therefore could be considered part of the VAE. With MoSys providing the performance scaling, and in an FPGA implementation, the hardware scaling with the Common RTL interface (VAE IF shown in the diagram).
New software can utilize the VAE API directly, achieving the highest level of performance and portability. Often the designer must work with existing software, which will require a different method to address.
The adaptation code has an API that is customer-specific and allows the customer to protect the transportability of the code to different hardware environments base on application performance needs.
For example, a packet classification could be implemented as a Virtual Accelerator and be deployed at different points in the stack and different points in the network all with the same software control API where some instances are pure software on a CPU all the way to hardware accelerator. Having the same common API enables portability of higher-level platform functionality. As new HW accelerator technology emerges, there is an increased probability that it can be utilized without disrupting the layers above, thus providing future proof path to increased performance scaling and capacity.
Utilizing the concept of common API and a virtual function, the VAE architecture can be used in hierarchical systems where the exist parallel paths processing packets from a fast path to slower paths. The benefit of the common API is that the same software stack can be used to control each of the paths in the hierarchy in a unified fashion.
MoSys is working with early access customers.
If you would like a demonstration of this technology, please contact us.