Introduction to the MoSys Accelerator Engine Strategy

MoSys provides multiple Acceleration Engine strategies to address a wide range of applications.

Accelerator Engine (Silicon ICs)

  • The Blazar family of Accelerator Engines are memory ICs which utilize a high speed serial (SerDes) interface with densities from 512Mb to 1Gb in size.
  • Intelligence is added by embedding functions into the memory that industry standard implementations take multiple cycles to accomplish, which results in accelerating system performance.
    • Bandwidth Engines (BE) are devices with embedded functions, several versions are available that also embedded ALU capability.
    • Programable HyperSpeed Engine (PHE) is a Bandwidth Engine with 1Gb of memory with 32 RISC computer cores.
  • Key benefits of an Accelerator Engine is the focus on applications needing:
  • Random memory access
  • Simplified board layout with few pins, from 8 to 64
  • High bandwidth
  • The ability to execute routines to reducing FPGA resources and improve system throughput

Virtual Accelerator Engine (Software/Firmware/Hardware)

  • Virtual Accelerator Engines (VAE) are designed to support a functional platform for example, a “Packet Filtering Platform”.
  • It is “Virtual” because it can be standalone software, FPGA RTL, or embedded Firmware based. Using MoSys’ common software interface (API) across multiple hardware environments, enables system designers to reuse internally developed software code to tune the performance required.
  • In addition, all FPGA-based VAEs use a common RTL IF that allows hardware transportability.
  • A VAE with a common API can run on:
    • CPU
    • Common FPGA RTL
      • FPGA that is not attached to a MoSys IC
      • FPGA that is attached to a member of the MoSys Accelerator Engine IC.
    • Performance scaling from a CPU only to a FPGA attached to a MoSys IC, can be as high as 100 times.
  • Key benefits of a Virtual Accelerator Engine is the focus on applications needing:
    • Protection of software investment with common API for transportability
    • Performance scaling over many different hardware environment
    • By designing to a common API, this allows a system designer to seamlessly port it across a range of performance platforms

Reference Links

MoSys’ new Software Accelerator Product Line is comprised of Function Accelerator Platforms, targeted at specific application functions where the platforms’ common software interface allows performance scalability over multiple hardware environments from CPU only to a range of FPGA performance solutions that use a common RTL I/F.  This software defined, hardware accelerated platform architecture allows users to preserve and re-use software assets via a common software interface and then depending on the performance needed, select the appropriate hardware environment.

As markets continue to migrate to software-defined environments, most notably software-defined networks (SDN), performance scaling has become key to remaining competitive while addressing the growing demands being placed on the network. Software investments now must be transferrable across multiple hardware environments in order to be both cost-effective and to provide the required flexibility to meet changing performance demands.

A Function Acceleration Platform is hardware agnostic and operates with or without a MoSys IC. For example, on a CPU or FPGA not attached to a MoSys IC, or an FPGA attached to a member of the MoSys Accelerator Engine IC family like the Bandwidth Engine or Programmable HyperSpeed Engine with in-memory compute capability. MoSys expects acceleration performance scaling across these platforms to be as high as 100x over standalone CPU implementations with an FPGA connected to a MoSys PHE. MoSys scalable solutions can meet today’s application needs, as well as flexibly provide a path to new products to address new and more performance-driven market demands.

Technical Overview:

At the core of providing a highly scalable platform is virtualizing the accelerator function by creating a functional abstraction with a high-level software API for a specific application area that can be implemented across different hardware and software environments. MoSys calls this a Virtual Accelerator Engine (VAE).

The VAE leverages a common application program interface (API) to enable a platform to achieve performance scaling of up to 100x. The same functions can scale from software running on a CPU; RTL running on an FPGA to very high-performance implementations which combine an FPGA connected to MoSys Accelerator Engine ICs with in-memory compute.

Virtual Accelerator Engine – Key Features

  • Single Common API
  • Single Common RTL Interface
  • Performance Scalability Across Multiple Hardware Environments
  • Adaptation Software

Single Common API:

A Virtual Accelerator Engine (VAE) employs a common application program interface (API) to allow for platform solutions portability of a given accelerator function. Implementations can range from software on a CPU, to modules in FPGAs, to very high-end, highly accelerated solutions using FPGAs with MoSys Accelerator Engine ICs like the MoSys PHE with its 32 RISC cores and 1Gb of embedded memory. A performance increase of a PHE implementation would be 100x over a CPU only solution.

Single Common RTL Interface

Most VAE platforms will have FPGA-based products with different performance capabilities. The RTL interface across these FPGA products will have a Common RTL logic specification (VAE IF).

Designing to a common hardware interface allows for easy migration between different performance and capacity requirements. Additionally, the designer can create a wider range of product offerings and can more easily implement add-on acceleration modules. This provides future proofing because as new silicon becomes available with a VAE port, the designer can drop it into the same logical “socket”.

Performance Scalability Across Multiple Hardware Environments

Scalability comes from the ability of each implementation to take advantage of available compute and memory resources. Memory can range from DRAM adjacent to the CPU, to block memory or HBM on the FPGA or 1T-SRAM tightly coupled with 32 RISC engines in MoSys Accelerator Engine IC products.

The common API is presented to the common s/w (“C VAE IF) or across different FPGA configurations with the common RTL (VAE IF).

Adaptation Layer Software

Implementation of a VAE will require an Adaptation Layer.

The adaptation layer provides a way for upper levels of software with an existing API to bridge to the VAE common API. The designer may develop their own adaption software libraries or choose to use software provided by MoSys as part of application specific platform.

If the user’s Adaptation Layer is included in every system, the Application API would be common across different hardware environment, and therefore could be considered part of the VAE. With MoSys providing the performance scaling, and in an FPGA implementation, the hardware scaling with the Common RTL interface (VAE IF shown in the diagram).

Embedded functions that can be benefit from this technology:

  • Key value pair databases
  • Networking search functions
  • Machine Learning
  • Computation
  • Algorithm acceleration
  • Security analysis
  • And more

Target markets where these functions are used include:

  • Smart NICs
  • Security appliances
  • Network hardware
  • Datacenter acceleration cards
  • 5G edge compute
  • Defense and aerospace
  • High-performance computing
  • High speed test equipment
  • And more

MoSys initial focus is on embedded applications that require:

  • High random-access rate memory
  • High data rate throughput
  • Low latency

Download the white paper here:  Virtualized Accelerator Engine

MoSys is working with early access customers.

If you would like a demonstration of this technology, please contact us.