BURST Accelerator Engine ICs
- 576 Mb memory with SerDes I/O
- Accessible through as few as 4 Lanes and as many as 16
- Deterministic Latency
- Embedded In Memory Functions
- Burst 2, 4 or 8 (EMIF)
- Two Separate Access Ports
- Full Production Qualified and Available
Superior, High Speed Random Access Memory Architecture
The heart of the memory IC is our advanced & parallel array of 1-T SRAM with a capacity of 576Mb.
- The memory is divided into 4 partitions allowing parallel (simultaneous) access. Each partition has 64 banks.
- There are two independent I/O ports per device, allowing for several memory access as well as multiple EIMFs to be executed in the same timeframe.
- Can be used as a Dual-Port memory
The tRC is 2.67 ns allowing up to 2.5 billion transactions per second.
Fixed In-Memory BURST Functions
The BURST Functions are focused on DATA MOVEMENT to accelerate getting data in and out of the memory faster and more efficiently by reducing the number of command cycles.
The BURST Read/Write In-Memory Functions can combine up to 8 READS and 8 WRITES into a single BURST command. This reduces the number of command cycles when moving data, nearly tripling the amount of data that can be moved in the same timeframe.
The Accelerator Engine can do several BURST Functions simultaneously, further increasing system performance.
High-Speed Serial Protocol I/O Interface
MoSys’s Accelerator Engines are designed using 16 SerDes lanes that can transmit data up to 12.5Gbps, with an optional rate of 10Gbps. MoSys’ GigaChip Interface (GCI) delivers full duplex, CRC protected data throughput, enabling up to 2.5 billion memory transaction per second on as few as 16 SerDes Lanes.
Traditional memory design requires many more interface pins (in some cases 1000s of pins), making signal routing and integrity a design challenge.
Each Accelerator Engine has 2 independent, 8 lane, I/O ports that allow simultaneous memory access operations.
The Ideal Replacement for Your Current QDR SRAM
QDR, SRAM provides speed and bandwidth, however the fact that sometimes designers need multiple devices with the high signal pin count needed to get the performance you’re looking for. MoSys multiport, serial, single-transistor SRAM eliminates all of these issues.
One MoSys device, replaces multiple QDR SRAMs.
Easy to Design-In
- Fewer pins using serial I/O with the GigaChip Interface technology
- Clean and reliable signal integrity board layout
- Standard replacement for QDR
- Simple to understand EIMF (Embedded In-Memory Functions) to accelerate performance
- High speed random access memory, with easy to understand EIMFs, with so fewer signal pins
- Architected to allow for a straight-forward design-in process
Bandwidth Engine 2 – BURST Architecture
Understanding MoSys’ Advanced 1T-SRAM Technology
Parallel Array Architecture
- 16 outstanding transactions
- 3.75 Billion Transactions per Second (2.5B Reads & 1.25B Writes)
- 160Gbps full duplex throughput
- 16ns deterministic read latency
- 2.67ns Random Cycle time (tRC)
- 90% efficient throughput
- Up to 16 low-latency SerDes lanes (10.3125Gbps or 12.5Gbps)
Single-Cell SRAM 70x better SER
- Full ECC support
- CRC protected and self-recovering
- SEU resistant
BE2-BURST Embedded In-Memory BURST Functions
Burst functions are designed to get data in and out of the memory more efficiently by reducing the number of commands. Normal transmission requires one command for each transfer of data. However, by bundling eight data words to a single command, designers can eliminate seven unnecessary commands. The BURST commands enable the transmission of 2, 4 or 8 words* per command cycle.
* word = 72 bits
|SerDes Speed Grade|
|Width||BURST||Throughput (Gbps)||Throughput (Gbps)|
* Low Power Option