Adds MoSys’ 1T-SRAM embedded memory for 0.15- and 0.13-micron standard logic processes

HSINCHU, TAIWAN and SUNNYVALE, CALIFORNIA (September 24, 2001) – UMC (NYSE:UMC) and MoSys (NASDAQ: MOSY) announced they have extended their cooperation to offer ultra-high density 1T-SRAM memories to UMC’s foundry customers, by porting MoSys’ 1T-SRAM memory technology to UMC’s 0.15- and 0.13-micron standard logic processes.
This builds on the earlier successful porting and silicon verification of MoSys’ 1T-SRAM memory to UMC’s 0.18-micron standard logic process.

“As customers demand increased density for embedded memory, MoSys is committed to ensuring that 1T-SRAM memory is available on the latest processes to facilitate the design of their next generation of products,” noted Mark-Eric Jones, vice president and general manager of intellectual property at MoSys.
“We are pleased to work with UMC to extend the availability of 1T-SRAM macros to UMC’s advanced logic processes.”

By using a single transistor bit cell, MoSys’ 1T-SRAM memory delivers embedded memory macros with double the density of traditional SRAM, while still delivering the fast random access cycle performance required by today’s System-on-Chip (SoC) designs.
The use of the standard logic process permits designers to economically embed large quantities of memory in the process that is optimum for the logic circuitry of the SoC design.

“We are pleased to extend our relationship with MoSys in order to offer our customers cost-effective solutions for embedded memory,” commented Jean Tien, strategic marketing vice president of UMC.
“The combination of UMC’s advanced logic processes and MoSys’ 1T-SRAM technology provides designers with a strong technology platform for their next generation of SoC products.”


Founded in 1991, MoSys develops, licenses and markets innovative memory technology for semiconductors. MoSys’ patented 1T-SRAM technology offers a combination of high density, low power consumption, high speed and low cost unmatched by other available memory technologies.
The single transistor bit cell used in 1T-SRAM technology results in the technology achieving much higher density than traditional four or six transistor SRAMs while using the same standard logic manufacturing processes.
1T-SRAM technology also offers the familiar, refresh-free interface and high performance for random address access cycles associated with traditional SRAMs.
In addition, this technology can reduce operating power consumption by a factor of four compared with traditional SRAM technology, contributing to making it an ideal technology for embedding large memories in System on Chip (SoC) designs.
1T-SRAM technology is in volume production both in SoC products at MoSys’ licensees as well as in MoSys’ standalone memories. MoSys is headquartered at 1020 Stewart Drive, Sunnyvale, California 94085.
More information is available on MoSys’ website at


UMC, a world leading semiconductor foundry, operates multiple wafer fabs in Taiwan’s Hsinchu Science Park. UMC’s Japanese subsidiary, Nippon Foundry Inc., has one fab in Japan, and UMC’s joint venture with Hitachi, Trecenti Technologies, began pilot production in its 300mm fab in Japan in 2000.
UMC’s 300mm facility in Taiwan’s Tainan Science Park began pilot production in June 2001, and the company has begun construction on UMCi, a third 300mm fab based in Singapore. UMC is a leader in foundry technology, with facilities that reached an annual output of more than 2.4 million eight-inch equivalent wafers in 2000 and shipped more silicon wafers in 0.18 micron and smaller technologies than any other foundry that year.
UMC’s 0.13 micron process combines up to 8 copper metal layers with true low-k dielectric materials. UMC serves customers around the world through sales and marketing offices located in the United States, Japan, and the Netherlands. UMC can be found on the web at


Note for Editors:

1T-SRAM is a trademark of MoSys,
Inc. All other trademarks or registered trademarks are the property
of their respective owners.