By Mark-Eric Jones, VP/ General Manager,
Intellectual Property, MoSys, Inc. Sunnyvale, Calif.

SUNNYVALE, Calif., March 15, 1999— In the system-chip
era, as much as 40 percent of die area will consist of memory, with
most of that being embedded RAM. Unfortunately, current embedded
memory technologies have failed to meet the needs of many system-chip
designs, and this often results in memory ending up off-chip after
analysis of the tradeoffs. Worse yet, many designers still view
embedded memory as a commodity technology with only small differences
between competing products. In reality, though, embedded memory
should be separated into “commodity IP” and “differentiated
IP,” in the same way IP is categorized for microprocessors
or peripherals. Failing to recognize this important distinction
with embedded memory can limit designers’ opportunities for product
differentiation and most importantly, performance.

Differentiated IP generally represents a unique (typically patent-protected)
architecture that provides users with functionality they could not
otherwise readily achieve. In contrast, commodity IP provides proven
building blocks for commonly available functions, primarily delivering
time-to-market advantages. While some of the more exotic non-volatile
and specialty memories can be highly differentiated, what about
the humble RAM that forms the majority of embedded memory requirements?

Differentiation in IP can occur in the four dimensions of function,
speed, area and power consumption. Often these dimensions interact.
For example, improving speed can result in a degradation of one
or more of the other dimensions such as power consumption or area.
Although some RAMs offer functional differentiation, the key areas
in which differentiation can exist are the trade-offs between the
remaining three dimensions.

Designers have had to choose between SRAM technology, which offers
the speed required by most systems but suffers from considerable
power consumption and area penalties, or embedded DRAM technology.
Although embedded DRAM technology overcomes the area and power consumption
penalties, it does so at an order of magnitude slower random cycle
speed, and it requires a more complex interface as well as costly
additions to the standard wafer fabrication process. The result
of these technology limitations is that each commodity embedded
memory technology ends up offering a different set of trade-offs.
Embedded SRAMs tend to be offered in high-speed, low-power or high-density
families. Although these pre-defined families offer the designer
a considerable time-to-market advantage, since the designs have
already been optimized in the desired direction, they are all based
on the same six-transistor cell technology.

One example of highly differentiated IP for embedded memory is
MoSys’ 1T-SRAM technology. This unique technology builds
memories with the refresh-free interface and SRAM random cycle speed
from single-transistor cells, giving significant area and power
consumption advantages over commodity six-transistor cell SRAM designs.
In addition, the memories can be fabricated on a completely standard
CMOS pure logic process, without the additional cost and process
complexity required for embedded DRAM technologies. Having been
proven in high volume production shipments of MoSys’ discrete SRAM
products, this patented architecture is now being licensed for the
embedded memory market.

To date, many SoC designs have not been able to economically embed
the quantity of RAM that would be desirable from a systems architecture
perspective, resulting in compromises and some solutions using off-chip
memories. Systems designers have an almost insatiable appetite for
memory, so it¹s not surprising to see that they readily translate
the density advantages of single-transistor SRAM into increased
on-chip memory. This increased on-chip memory often allows designers
to differentiate their products with higher performance and increased
functionality, rather than to solely reduce cost.

The ability to embed megabytes of high performance SRAM memory
in a single chip will be an enabler for tomorrow’s enhanced system
architectures. The high density combined with SRAM performance allows
the simplification of today’s multilevel cache and main memory hierarchies.
This in turn allows designers to focus on value-added functionality
rather than overcoming the shortcomings of embedded memory technology.
More importantly, this type of differentiated embedded memory IP
can enable SoC product designs that would otherwise not have been
economically feasible, opening up new market opportunities. In the
end, this is where using a differentiated memory technology can
deliver the greatest value to designers.



Mark-Eric Jones is Vice President & General Manager
of Intellectual Property for MoSys, Inc. in Sunnyvale, California,
an advanced memory technology company. Previously he managed Mentor
Graphics’ “Inventra” IP business. He was CEO and founder
of 3Soft, which was one of the first businesses to adopt the silicon
IP business model in 1988. He was involved in founding RAPID (the
IP industry business association) in 1996 and currently serves as
chairman of its board of directors. He received an M.A. degree in
Electrical Sciences from the University of Cambridge, England.