MoSys Unveils Ultra-High Reliability 1T-SRAM-R Embedded Memory Technology

Transparent Error Correction increases density and quality, eliminating costs of laser repair and Error Checking and Correction

SUNNYVALE, CALIFORNIA (January 28, 2002) – MoSys (NASDAQ:MOSY) today announced its 1T-SRAM-RTM embedded memory technology option for high performance integrated circuits in communications and other applications that require very high reliability, immunity to soft errors and lowest manufacturing cost. Fabricated in standard logic processes and employing the same, simple, industry-standard SRAM interface, 1T-SRAM-R memory macros can directly replace other embedded SRAMs, achieving lower cost and higher reliability without changes to system design.

1T-SRAM-R memories are the first embedded memories to incorporate Transparent Error CorrectionTM (TECTM), a MoSys patented technology that eliminates the need for laser repair during manufacture or self-repair at power-up. Transparent Error Correction technology dynamically corrects both hard and soft errors, repairing silicon defects that occurred during as well as after the manufacture of the chip, therefore improving the yield and reliability of devices incorporating 1T-SRAM-R macros. Transparent Error Correction allows 1T-SRAM-R memories to achieve Soft Error Rates (SER) of less than 10 FIT/Mbit in 0.13-micron technology, three orders of magnitude better than traditional SRAMs, resulting in dramatically improved system-level reliability.

“Designer’s of the next generation of System-on-Chip products are being challenged to overcome the rapidly increasing soft error rates of six or four transistor SRAMs in deep sub-micron processes,” commented Mark-Eric Jones, MoSys’ vice president and general manager of intellectual property, “Our production-proven 1T-SRAM embedded memory already offers measured soft error rates that are significantly better than other SRAM technologies. Going forward, our 1T-SRAM-R option now enables soft error rates to be reduced by a factor of one thousand or more without the twenty to thirty percent cost penalty required to implement Error Checking and Correction (ECC) circuits for other SRAMs.”

Transparent Error Correction achieves these quality and reliability advantages without the traditional die-area and cost penalties associated with ECC, while still meeting standard logic design rules. By also including all the error correction circuitry within the macro, Transparent Error Correction technology provides the industry-standard SRAM interface and maintains the high performance required by leading-edge applications. In addition to the proven yield and cost advantages offered by 1T-SRAM technology, Licensees using MoSys’ 1T-SRAM-R macros will realize additional product cost savings due to the simplified manufacturing flow that eliminates the need for laser repair.


1T-SRAM-R memory macros are now available for standard logic processes starting with the 0.13-micron generation. Contact MoSys for pricing details for specific memory configurations.


Founded in 1991, MoSys develops, licenses and markets innovative memory technology for semiconductors. MoSys’ patented 1T-SRAM technology offers a combination of high density, low power consumption, high speed and low cost unmatched by other available memory technologies. The single transistor bit cell used in 1T-SRAM technology results in the technology achieving much higher density than traditional four or six transistor SRAMs while using the same standard logic manufacturing processes. 1T-SRAM technology also offers the familiar, refresh-free interface and high performance for random address access cycles associated with traditional SRAMs. In addition, this technology can reduce operating power consumption by a factor of four compared with traditional SRAM technology, contributing to making it an ideal technology for embedding large memories in System-on-Chip (SoC) designs. 1T-SRAM technology is in volume production both in SoC products at MoSys’ licensees as well as in MoSys’ standalone memories. MoSys is headquartered at 1020 Stewart Drive, Sunnyvale, California 94085. More information is available on MoSys’ website at

Note for Editors:

1T-SRAM® is a MoSys trademark registered in the U.S. Patent and Trademark Office. 1T-SRAM-RTM, Transparent Error CorrectionTM and TECTM are trademarks of MoSys. All other trademarks or registered trademarks are the property of their respective owners.