Bandwidth Engine 2 – Macro Accelerates Metering, Statistics, Accounting and Atomic Operations
As network performance and feature requirements continue to scale, architectural improvements are required. Networking equipment has transitioned to highly parallel, multi-threaded processing System-on-Chip complexes which require an insatiable amount of memory bandwidth. The Bandwidth Engine 2 family has three purpose-built variants, Burst, Access and Macro, to meet these growing needs and is intended for high-reliability, carrier-grade applications.
Using sixteen 15 Gigabits per second (Gbps) SerDes lanes, the Bandwidth Engine 2 interface operates at 480 Gbps, providing the host with up to 384 Gbps CRC protected, effective data throughput. This represents an unprecedented 80% overall efficiency, well beyond the capability of standard memory subsystems and alternative serial interface solutions, while using less than half of the board area, interface pins, and power resulting in substantial system-level cost savings.
The new device, MSR820, with its on-board accelerators, is capable of fire-forward operations which can update records entirely internal to the device, reducing the number of memory bus transactions from six down to one, as well as relieving the host of the computations required for the update. The MSR820’s macros can be saturated using only 8 SerDes lanes, further reducing the power, pincount and host resources. The macro functions can retire entire operations in under 30 nanoseconds (ns), far quicker and at substantially lower power than alternative solutions, making Bandwidth Engine 2 – Macro a device unique to the industry in its capabilities.
“The industry is challenged to provide high-performance line cards that can aggregate hundreds of Gigabytes of bandwidth and deliver ever increasing intelligence,” stated
MoSys’ Bandwidth Engine family of ICs utilizes the GigaChip™ Interface, an open, 90% efficient, reliable transport protocol optimized for chip-to-chip communications. The devices are compatible with CEI-11G and XFI SerDes, which allows a seamless interface with high performance FPGAs as well as standard libraries available from ASIC providers. A complete package of RTL and tools is available to support the Bandwidth Engine interface.
This press release may contain “forward-looking statements” about
Forward-looking statements are based on certain assumptions and expectations of future events that are subject to risks and uncertainties. Such statements are made in reliance upon the safe harbor provisions of Section 27A of the Securities Act of 1933 and Section 21E of the Securities Exchange Act of 1934. Actual results and trends may differ materially from historical results or those projected in any such forward-looking statements depending on a variety of factors. These factors include, but are not limited to:
- customer acceptance of Bandwidth Engine ICs;
- difficulties and delays in the development, production, testing and marketing of ICs;
- the anticipated costs and technological risks of developing and bringing ICs to market;
- the willingness of our manufacturing partners to assist successfully with the fabrication of ICs;
- the availability of quantities of ICs supplied by our manufacturing partners at a competitive cost;
and other risks identified in