SANTA CLARA, Calif., Mar 15, 2011 (BUSINESS WIRE) — MoSys (NASDAQ: MOSY):
Who: MoSys (NASDAQ: MOSY), a leading architect of serial chip-to-chip communications solutions that deliver unparalleled bandwidth performance for next generation networking systems and advanced system-on-chip (SoC) designs, presents an on-demand, webcast titled, “Meeting Chip to Chip I/O Demands of 100G and Beyond Line Cards,” hosted on the company’s website at www.mosys.com/eventCalendar.php.
The webcast’s panel is introduced and moderated by Andrew Schmitt, Directing Analyst, Optical, Infonetics Research. MoSys’ Vice President of Technology Innovation and System Applications, Michael Miller, is joined by fellow panelists from Avago Technologies, Cadence Design Systems and Xilinx, Inc.
What: The on-demand webcast, “Meeting Chip to Chip I/O Demands of 100G and Beyond Line Cards,” delves into line card designs focusing on how to achieve packet forwarding beyond 100 Gbps. With the bandwidth density of the line card increasing and the interface between devices on the line card such as the NPU, memory and communication interface becoming more challenging, the traditional DDR/QDR single-ended interfaces will become extremely difficult to design with beyond the 2.133 GHz because of pin counts, tight layout and timing constraints. As a result, designers need to rethink packet processing and memory subsystems, the division of labor and the interconnect topology. This panel explores trends and alternative solutions for interconnecting chips on 100 Gbps and beyond line cards that maximize throughput while minimizing pin count, die area and power.
When: The webcast is now available on MoSys’ website.
Where: Exclusively available at www.mosys.com/eventCalendar.php
About MoSys, Inc.
MoSys, Inc. (NASDAQ: MOSY) is a leading architect of serial chip-to-chip communications solutions that deliver unparalleled bandwidth performance for next generation networking systems and advanced system-on-chip (SoC) designs. MoSys’ Bandwidth Engine(TM) family of ICs combines the company’s patented 1T-SRAM® high-density memory technology with its high-speed 10 Gigabits per second (Gbps) SerDes interface (I/O) technology. A key element of Bandwidth Engine technology is the GigaChip(TM) Interface, an open, CEI-11 compatible interface developed to enable highly efficient serial chip-to-chip communications. MoSys’ IP portfolio includes SerDes IP and DDR3 PHYs that support data rates from 1 – 11 Gbps across a variety of standards. In addition, MoSys offers its flagship, patented 1T-SRAM and 1T-Flash® memory cores, which provide a combination of high-density, low power consumption, high-speed and low cost advantages for high-performance networking, computing, storage and consumer/graphics applications. MoSys IP is production-proven and has shipped in more than 370 million devices. MoSys is headquartered in Santa Clara, California. More information is available on MoSys’ website at www.mosys.com.
MoSys, 1T-SRAM, 1T-Flash and Bandwidth Engine are registered trademarks of MoSys, Inc. in the US and/or other countries. The MoSys logo and GigaChip are trademarks of MoSys, Inc. All other marks mentioned herein are the property of their respective owners.