SUNNYVALE, Calif.–(BUSINESS WIRE)–Nov. 24, 2003–MoSys, Inc.
(Nasdaq:MOSY) the industry’s leading provider of high density SoC
embedded memory solutions today announced the initial silicon
verification of MoSys’ 1T-SRAM-R(TM) memory technology on NEC
Electronics’ 90-nanometer standard logic process. Silicon testchips
for MoSys’ quad density 1T-SRAM-Q(TM) embedded memory technology are
also currently being manufactured on NEC Electronics’ 90-nanometer
logic process. This represents the latest milestone in a successful
relationship between the companies on multiple process generations and
memory technologies starting in 1999.

“Today’s system level LSI designers need to efficiently embed more
and more memory in their designs to reach the difficult performance
and power requirements demanded by their markets,” said Hirokazu
Hashimoto, executive vice president at NEC Electronics Corporation,
“We are very pleased to reach this new milestone in our cooperation
with MoSys to bring its latest embedded memory technologies to our SoC
customers.”

“MoSys has already very successfully partnered with NEC
Electronics to deliver leading-edge SoC embedded memory solutions in
high volume,” commented Mark-Eric Jones, vice president and general
manager of Intellectual Property at MoSys “We look forward to
continuing and broadening this relationship to enable NEC Electronics’
90-nanometer logic process customers to take advantage of our latest
1T-SRAM-Q and 1T-SRAM-R technologies for their SoC designs.”

ABOUT 1T-SRAM-Q

1T-SRAM-Q technology is the latest offering from MoSys as part of
their embedded memory solutions. 1T-SRAM-Q achieves its exceptional
density by using bit cells of just 0.3 micron2 in the 90-nanometer
logic process. Using only one additional, non-critical mask on the
standard logic process, 1T-SRAM-Q enables cost-effective integration
of large amounts of embedded memory on SoC designs without any change
to the other logic IP blocks or libraries. 1T-SRAM-Q incorporates
MoSys’ proprietary Transparent Error Correction(TM) (TEC(TM))
technology delivering the additional benefits of improved yield and
reliability with elimination of laser repair and soft error concerns.

About MoSys

Founded in 1991, MoSys (Nasdaq:MOSY), develops, licenses and
markets innovative memory technologies for semiconductors. MoSys’
patented 1T-SRAM technologies offer a combination of high density, low
power consumption, high speed and low cost unmatched by other
available memory technologies. The single transistor bit cell used in
1T-SRAM memory results in the technology achieving much higher density
than traditional four or six transistor SRAMs, while using the same
standard logic manufacturing processes. 1T-SRAM technologies also
offer the familiar, refresh-free interface and high performance for
random address access cycles associated with traditional SRAMs. In
addition, these technologies can reduce operating power consumption by
a factor of four compared with traditional SRAM technology,
contributing to making it ideal for embedding large memories in System
on Chip (SoC) designs. MoSys’ licensees have shipped more than 50
million chips incorporating 1T-SRAM embedded memory, demonstrating the
excellent manufacturability of the technology in a wide range of
silicon processes and applications. MoSys is headquartered at 1020
Stewart Drive, Sunnyvale, California 94085. More information is
available on MoSys’ website at http://www.mosys.com.

Note for Editors:

1T-SRAM(R) is a MoSys trademark registered in the U.S. Patent and
Trademark Office. All other trade, product, or service names
referenced in this release may be trademarks or registered trademarks
of their respective holders.

SOURCE: MoSys, Inc.