SANTA CLARA, Calif., Nov 03, 2010 (BUSINESS WIRE) —
MoSys, Inc. (NASDAQ: MOSY):
MoSys (NASDAQ: MOSY), a leading architect of serial chip-to-chip communications solutions that deliver unparalleled bandwidth performance for next generation networking systems and advanced system-on-chip (SoC) designs, is participating at The 8th International System-on-Chip (SoC) Conference, Exhibit and Workshops. Mark Baumann, Director, Product Definition and Applications at MoSys, will be presenting “Breaking Bandwidth Density Barriers with GigaChipTM Serial Interface and the Bandwidth EngineTM” in the Emerging Technologies, Trends and Possibilities Multicore SoC Platforms track at 3:50 p.m. – 4:20 p.m. on November 3, 2010
The 8th International SoC Conference, Exhibit and Workshops offers two days of technical presentations, panel discussions, tabletop exhibits, tutorials, and a variety of technical workshops. Over the past 7 years, the International SoC Conference has established itself as the premier annual event for System-on-Chip and VLSI. The Conference provides an outstanding platform for sharing and disseminating groundbreaking research, revolutionary product announcements, and innovative technical tutorials, and it has established itself as the forum for debating emerging challenges in System-on-Chip, VLSI, and Nanotechnologies.
November 3-4, 2010
On Wednesday, November 3, the conference will be held from 8 a.m. – 5 p.m. Exhibits will be open from 3 p.m. to 8 p.m. On Thursday, November 4, the conference occurs from 8 a.m. – 7 p.m.
Hilton Irvine/Orange County Airport
|18800 MacArthur Blvd.|
|Irvine, CA 92612|
About MoSys, Inc.
MoSys, Inc. (NASDAQ: MOSY) is a leading architect of serial chip-to-chip communications solutions that deliver unparalleled bandwidth performance for next generation networking systems and advanced system-on-chip (SoC) designs. MoSys’ Bandwidth Engine(TM) family of ICs combines the company’s patented 1T-SRAM(R) high-density memory technology with its high-speed 10 Gigabits per second (Gbps) SerDes interface (I/O) technology. A key element of Bandwidth Engine technology is the GigaChip(TM) Interface, an open, CEI-11 compatible interface developed to enable highly efficient serial chip-to-chip communications. MoSys’ IP portfolio includes SerDes IP and DDR3 PHYs that support data rates from 1 – 11 Gbps across a variety of standards. In addition, MoSys offers its flagship, patented 1T-SRAM and 1T-Flash(R) memory cores, which provide a combination of high-density, low power consumption, high-speed and low cost advantages for high-performance networking, computing, storage and consumer/graphics applications. MoSys IP is production-proven and has shipped in more than 325 million devices. MoSys is headquartered in Santa Clara, California. More information is available on MoSys’ website at https://dev-mosys-web-04-19.pantheonsite.io.
MoSys, 1T-SRAM and 1T-Flash are registered trademarks of MoSys, Inc. The MoSys logo, Bandwidth Engine and GigaChip are trademarks of MoSys, Inc. All other marks mentioned herein are the intellectual property of their respective owners.
SOURCE: MoSys, Inc.