High-Speed SATA IP Broadens MoSys Portfolio of Mixed-Signal IP

SUNNYVALE, Calif., Nov. 15 /PRNewswire-FirstCall/ — MoSys, Inc.
(Nasdaq: MOSY), a leading provider of high-density embedded memory and
mixed-signal intellectual property (IP) solutions, today announced the
availability of two new Serial ATA (SATA) Physical Layer (PHY) IPs: MoSys’s
SATA GEN II PHY IP and GEN I PHY IP. The announcement follows the recent
introduction of the Gigabit Ethernet PHY as the latest in the company’s
portfolio of mixed-signal IP. The SATA PHY IP is targeted at the home
entertainment, storage, storage area network (SAN), network attached storage
(NAS), and PC markets.

The MoSys SATA GEN II (3.0Gbs) PHY IP is compliant with Serial ATA II
Electrical Specification Revision 2.5 and is backward compatible to the widely
deployed Gen I (1.5GbS) Serial ATA standard. Key functions integrated into the
IP include the use of Out-Of-Band Signaling (OOB) protocol for initializing
the SATA Interface to execute a pre-defined speed negotiation function.
Digital clock and data recovery (CDR) with digital equalization, spread
spectrum clocking, optional 8B/10B encoder & decoder, programmable
pre-emphasis and swing control, with low power consumption of less than 150mW
per channel make the IP ideal for integration into highly complex ASSP, ASICs
and SoCs. The SATA Gen II is currently designed in 130nm General (G) and Low
Voltage (LV) CMOS processes and plan to be retargeted to 65nm and 45nm process
nodes. A complete high speed network to storage solution can now be created
utilizing the MoSys Gigabit Ethernet PHY IP together with the SATA GEN II

The Serial ATA Gen I PHY design is compliant with the requirements stated
in the Serial ATA standard, rev 1.0a. The IP is designed in 180nm and 130nm
General (G) processes and can be readily ported to 65nm and 45nm technologies.
The PHY IP core has an Out Of Band (OOB) processor to initialize the link, a
digital clock and data recovery (CDR) with digital equalization, spread
spectrum clocking, optional 8B/10B encoder and decoder at a low power
consumption of less than 75mW per channel.

“Our SATA PHY IP offering is our second strategic move into the
mixed-signal IP market,” stated Max Bathaee, Director of Mixed-Signal
Marketing at MoSys. “The focus of this IP was to develop a highly robust and
compatible PHY that could easily be integrated into a range of solutions.
With our previously announced Gigabit Ethernet PHY, we now offer our customers
two critical blocks of mixed-signal IP from one source, ensuring rapid,
risk-reduced designs.”

Proven in silicon, both SATA PHY IPs are available now to pure play
foundries, IDMs and fabless semiconductor companies.


MoSys Inc. provides advanced memory and analog/mixed-signal IP for systems
on chips (SoC), enabling electronic products to achieve levels of integration
that would be impossible or impractical using conventional technology. The
company’s groundbreaking memory solutions include its patented 1T-SRAM(R) and
1T-FLASH(TM) technologies — high-density alternatives to traditional volatile
and non-volatile embedded memory. MoSys mixed-signal products feature a number
of industry firsts, including the first DVD front end IP to support both
Blu-ray (BD) and HD DVD formats. Using MoSys IP, system vendors can achieve
best-in-class price/performance in markets such as home entertainment and
graphics applications; mobile consumer devices; and networking and storage
equipment. To date, MoSys technology has been shipped in over 135 million
devices.MoSys was founded in 1991, and had its initial public offering in 2001
(Nasdaq:MOSY). The company is headquartered in Sunnyvale, California at 755 N.
Mathilda Avenue, Sunnyvale, California 94085. More information is available on
MoSys’ website at https://dev-mosys-web-04-19.pantheonsite.io.

1T-SRAM(R), 1T-FLASH(TM), and GigaCell(TM) are registered trademarks of
MoSys, Inc.

Sally Pedreiro
MoSys, Inc.
Sunnyvale, CA
+1 (408) 731-1832

Beverly Twing, Acct. Manager
Shelton IR
+1 (972) 239-5119 x126

SOURCE MoSys, Inc. 11/15/2007