SANTA CLARA, Calif., Oct 05, 2011 (BUSINESS WIRE) — MoSys, Inc. (NASDAQ: MOSY):
MoSys (NASDAQ: MOSY), a leading provider of serial chip-to-chip communications solutions that deliver unparalleled bandwidth performance for next generation networking systems and advanced system-on-chip (SoC) designs, is a sponsoring exhibitor and a presenter at the Linley Tech Processor Conference.
MoSys’ VP of Technology Innovation and System Applications, Michael Miller, will be presenting, “Alleviating the Burden of Gathering Network Statistics.” Miller’s presentation will take place on October 6, 2011 during Session 9: Memory and Memory Alternatives. The session, moderated by Joseph Byrne, focuses on specialized memories for communications processing, and technologies that can substitute for these memories. Miller will discuss overall limitations as communications equipment moves to 100GE and beyond. He will specifically discuss MoSys’ GigaChip Interface and the macro instructions of the Bandwidth Engine® IC, which give system designers relief over other alternatives using traditional networking memory.
|The Linley Tech Processor Conference is a two-day event that will focus on processors and related technologies for networking and communications applications. Industry leaders will deliver in-depth information on the newest chips and technologies. Attendees will hear presentations addressing various types of processor architecture and design, semiconductor intellectual property, and related technologies used in these applications.|
|The Linley Tech Processor Conference takes place on October 5-6, 2011.|
|DoubleTree by Hilton Hotel|
|2050 Gateway Place|
|San Jose, Calif. 95110|
More information about MoSys’ participation at The Linley Tech Processor Conference and other upcoming conferences is available on its website at https://dev-mosys-web-04-19.pantheonsite.io/eventCalendar.php.
About MoSys, Inc.
MoSys, Inc. (NASDAQ: MOSY) is a leading provider of high-performance networking memory solutions and high-speed, multi-protocol serial interface intellectual property (SerDes IP). MoSys’ leading edge Bandwidth Engine® ICs combine the company’s patented 1T-SRAM® high-density memory with its SerDes IP and are initially targeted at providing breakthroughs in bandwidth and access performance in next generation networking systems. MoSys’ SerDes IP and DDR3 PHYs support a wide range of data rates across a variety of standards, while its 1T-SRAM memory cores provide a combination of high-density, low-power consumption, high-speed and low cost advantages for high-performance applications. MoSys is headquartered in Santa Clara, California. More information is available on MoSys’ website at https://dev-mosys-web-04-19.pantheonsite.io.
MoSys, 1T-SRAM and Bandwidth Engine are registered trademarks of MoSys, Inc. in the US and/or other countries. The MoSys logo and GigaChip are trademarks of MoSys, Inc. All other marks mentioned herein are the property of their respective owners.
SOURCE: MoSys, Inc.