SUNNYVALE, Calif.–(BUSINESS WIRE)–Jan. 20, 2004–MoSys, Inc.
(Nasdaq:MOSY), the industry’s leading provider of high density SoC
embedded memory solutions, announced today a range of embedded memory
products to help SoC designers reduce leakage in their 0.13-micron
chips. To complement existing high-density, low-leakage 1T-SRAM-M(TM)
and 1T-SRAM-MQ(TM) memory technologies, MoSys now offers compilers for
low-leakage 6T-SRAM-R(TM) memories to reduce the chip leakage caused
by other six-transistor embedded memories.
In generic 0.13-micron logic processes, replacing large
six-transistor memories with 1T-SRAM-M technology can reduce leakage
by more than a factor of four, in addition to the considerable die
size reduction. Using MoSys’ new 6T-SRAM-R technology compilers,
designers can also now reduce the leakage on the remaining
six-transistor memories by more than a factor of two, further
optimizing the total SoC leakage without compromising die size or
requiring special processes.
“Customers are very pleased with the quality and leakage
advantages offered by our 1T-SRAM(R) technologies for large memories
and asked MoSys to help them extend these benefits to the small
memories in their designs,” stated Dr. Fu-Chieh Hsu, MoSys’ president
and CEO. “In response, we developed our 6T-SRAM-R compiler which
delivers a new standard of quality, combined with much lower leakage
than other six-transistor embedded memories.”
In addition to leakage suppression, MoSys’ 6T-SRAM-R compiler
eliminates memory soft errors and the need for laser repair by
optionally including MoSys’ Transparent Error Correction(TM) (TEC(TM))
technology used in MoSys’ 1T-SRAM-R(TM) and 1T-SRAM-Q(TM) technologies
for applications requiring a high-level of quality and reliability in
smaller embedded memories.
Single-port and dual-port compilers covering 1- to 512-Kbit sizes
are being offered for MoSys’ low-leakage 6T-SRAM-R technology. Silicon
reports are available from MoSys.
Founded in 1991, MoSys (Nasdaq:MOSY), develops, licenses and
markets innovative memory technologies for semiconductors. MoSys’
patented 1T-SRAM technologies offer a combination of high density, low
power consumption, high speed and low cost unmatched by other
available memory technologies. The single transistor bit cell used in
1T-SRAM memory results in the technology achieving much higher density
than traditional four or six transistor SRAMs, while using the same
standard logic manufacturing processes. 1T-SRAM technologies also
offer the familiar, refresh-free interface and high performance for
random address access cycles associated with traditional SRAMs. In
addition, these technologies can reduce operating power consumption by
a factor of four compared with traditional SRAM technology,
contributing to making it ideal for embedding large memories in System
on Chip (SoC) designs. MoSys’ licensees have shipped more than 50
million chips incorporating 1T-SRAM embedded memory, demonstrating the
excellent manufacturability of the technology in a wide range of
silicon processes and applications. MoSys is headquartered at 1020
Stewart Drive, Sunnyvale, California 94085. More information is
available on MoSys’ website at https://dev-mosys-web-04-19.pantheonsite.io.
Note for Editors:
1T-SRAM(R) is a MoSys trademark registered in the U.S. Patent and
Trademark Office. All other trade, product, or service names
referenced in this release may be trademarks or registered trademarks
of their respective holders.
CONTACT: MoSys, Sunnyvale
K.T. Boyle, +1 408-731-1830
Shelton PR, Dallas
+1 (972) 239-5119×128
Billings PR, Europe, Oxfordshire, UK
Nick Foot, +44-1491-636393
SOURCE: MoSys, Inc.