MSR620 Delivers Highest Bandwidth Density Buffer for 100G Networking Line Cards and is Scalable to 400G
As network performance scales up and feature requirements increase to support hundreds of gigabit per second data traffic per line card, architectural improvements are required to ensure throughput performance, quality of service and data integrity. Using sixteen 15 Gigabits per second (Gbps) SerDes lanes, the MSR620 interface operates at 480 Gbps, providing the host with up to 384 Gbps CRC protected, effective data throughput. This represents an unprecedented 80% overall efficiency, well beyond the capability of standard memory subsystems and alternative serial interface solutions. A single MSR620 device can support up to 5 milliseconds of packet buffering for a 100 Gbps interface, smoothing transient peaks and allowing the traffic manager the time necessary to process and prevent lost packets. Alternative architectures often require highly complex and expensive board designs that result in more than twice the board area and power, which is neither available nor economical.
The MSR620 device is the first of MoSys’ second generation Bandwidth Engine architecture to be released and offers the highest data throughput for high-speed 100G to 400G packet buffer applications. Like its first generation predecessor, the Bandwidth Engine 2 family is designed to meet high reliability, carrier grade network equipment requirements. In addition to this base reliability, the second generation includes provisions for optional use of
“We are pleased to announce sample availability of the MSR620 Burst product,” said
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