Optimizes Second Generation Architecture for Dual Port SRAM Type Random Access performance in Packet Processing and State Memory Applications
The new device, MSR720, will extend Bandwidth Engine capabilities through the ability to simultaneously read and write to a specific memory location. The unique device architecture maintains full data coherency, high command efficiency and simplified scheduling, resulting in a performance of up to 4.5 Giga-Accesses per second (GA/s). The high access rates and reduced effective cycle time of the MSR720 access device are well suited to the requirements of state memory and queuing applications, where repeat access of the same address is needed.
Using 16 SerDes lanes at 15 Gigabits per second (Gbps), the MSR720 interface operates at 480 Gbps, providing the host with up to 270 Gbps CRC protected, effective data throughput. The device also supports 36-bit half-word write capabilities which improve the command bus utilization. The culmination of these features improves performance beyond the capability of standard memory subsystems, while occupying less board area, using fewer interface pins, and consuming less power.
Network system access rate requirements far exceed the access rate at which traditional solutions can enable real-time access to packet header data. The second generation Bandwidth Engine architecture will close this performance gap for customers with its MSR720 device architecture and will deliver on these requirements, resulting in the highest performance single chip networking memory solution available today.
“Our second generation Bandwidth Engine architecture will support purpose-built variants to optimize specific applications and access types,” stated
MoSys’ Bandwidth Engine family of ICs utilizes the GigaChip™ Interface, an open, 90 percent efficient, reliable transport protocol optimized for chip-to-chip communications. The device is compatible with CEI-11G and XFI SerDes which allows a seamless interface with high performance FPGAs, as well as standard libraries available from ASIC providers. A complete package of RTL and tools is available to support the Bandwidth Engine interface.
This press release may contain “forward-looking statements” about
Forward-looking statements are based on certain assumptions and expectations of future events that are subject to risks and uncertainties. Such statements are made in reliance upon the safe harbor provisions of Section 27A of the Securities Act of 1933 and Section 21E of the Securities Exchange Act of 1934. Actual results and trends may differ materially from historical results or those projected in any such forward-looking statements depending on a variety of factors. These factors include, but are not limited to:
- customer acceptance of Bandwidth Engine ICs;
- difficulties and delays in the development, production, testing and marketing of Bandwidth Engine ICs;
- the anticipated costs and technological risks of developing and bringing ICs to market;
- the willingness of our manufacturing partners to assist successfully with the fabrication of Bandwidth Engine ICs;
- the availability of quantities of ICs supplied by our manufacturing partners at a competitive cost;
and other risks identified in