SUNNYVALE, Calif.–(BUSINESS WIRE)–Dec. 9, 2002–MoSys, Inc.
(NASDAQ:MOSY), a leading provider of high density SoC embedded memory
solutions, today announced the availability of its first 1T-SRAM(R)
memory compiler for TSMC and UMC 0.15-micron logic processes. The
compiler is a result of the combination of MoSys’ embedded memory and
advanced technology obtained through the acquisition of ATMOS
Corporation earlier this year. The MoSys memory compiler is
web-accessible and automatically generates a wide variety of design
views for MoSys’ 1T-SRAM memory, enabling design engineers to easily
and rapidly evaluate different memory configurations in their designs.

“The 1T-SRAM memory compiler combines proven expertise in
high-density memory compilers and industry leading 1T-SRAM technology
while also offering users the convenience of a Web-based tool,” stated
Wlodek Kurjanowicz, MoSys fellow. “The 0.15-micron 1T-SRAM compiler is
available to engineers wanting to incorporate 1T-SRAM macros into
their SOC designs today. In addition, the Company is in the advanced
stage of developing a compiler for the 0.13-micron process and plans
to offer compilers for smaller process nodes in the future.”

Available at no charge via MoSys’ Web site (,
the 1T-SRAM memory compiler gives design engineers complete control
when investigating various options and benefits of using 1T-SRAM
memory technology. The MoSys 1T-SRAM compiler provides design
engineers with front-end design information, such as datasheets, VHDL
and Verilog simulation models, as well as timing models for synthesis.
The compiler also allows design engineers to include 1T-SRAM macro
instances in their layout by providing interface signal connections in
place and route views. Following licensing of the design, the final
GDS2 database is delivered to the customer from MoSys.

Registered design engineers for the MoSys compiler can access as
many configurations as necessary, to find the one that best suits
their design needs. The compiler allows the user to select
specifications for the design, which include: memory size and
configuration (number of words and word size operating parameters,
speed and temperature range), interface timing options (pipelined or
flow-through read access, as well as options on write timing) and
choosing deliverable options. Based on this information, all the views
needed for simulation, synthesis, floor-planning and place and route
of their design are generated allowing design engineers to quickly
explore numerous “what if” scenarios. Following licensing of the
chosen 1T-SRAM macro design, the final GDS2 database is delivered to
the customer for merging into their tapeout.

“Our 1T-SRAM memory compiler is another way MoSys is enhancing
customer service and making our technology more accessible to a
broader range of designers. By making this tool available to engineers
through the Web, we are helping them instantly determine the best
possible solution for their chip design.” stated Mark-Eric Jones, vice
president and general manager of Intellectual Property, MoSys. “Now
that embedded memory plays such a critical role in the cost and
performance of most SOC designs, engineers need fast, easy access to
the best memory technologies.”

With the introduction of the 1T-SRAM compiler, MoSys now offers
customers a choice of options in design methodologies that include
compiled, full custom and off-the-shelf memory macros.


Founded in 1991, MoSys (NASDAQ: MOSY), develops, licenses and
markets innovative memory technologies for semiconductors. MoSys’
patented 1T-SRAM technologies offer a combination of high density, low
power consumption, high speed and low cost unmatched by other
available memory technologies. The single transistor bit cell used in
1T-SRAM technology results in the technology achieving much higher
density than traditional four or six transistor SRAMs while using the
same standard logic manufacturing processes. 1T-SRAM technologies also
offer the familiar, refresh-free interface and high performance for
random address access cycles associated with traditional SRAMs. In
addition, this technology can reduce operating power consumption by a
factor of four compared with traditional SRAM technology, contributing
to making it an ideal technology for embedding large memories in
System on Chip (SoC) designs. 1T-SRAM technologies are in volume
production both in SoC products at MoSys’ licensees as well as in
MoSys’ standalone memories. MoSys is headquartered at 1020 Stewart
Drive, Sunnyvale, California 94085. More information is available on
MoSys’ Web site at

1T-SRAM(R) is a MoSys trademark registered in the U.S. Patent and
Trademark Office. All other trade, product, or service names
referenced in this release may be trademarks or registered trademarks
of their respective holders.