MBISTArchitect users can now seamlessly support 1T-SRAM memory test
SUNNYVALE, CALIFORNIA (January 14, 2002) – MoSys, Inc. (NASDAQ:MOSY), the industry’s leading provider of the highest density System-on-Chip (SOC) embedded memory solutions and Mentor Graphics, a world leader in EDA solutions, including Design-for-Test (DFT), today announced their collaboration to qualify and deliver memory Built-In Self-Test (BIST) solutions optimized for the MoSys® 1T-SRAM® family of high-density embedded memories to reduce test cost.
MoSys and Mentor Graphics have verified the integration of 1T-SRAM embedded memories using the Mentor Graphics® MBISTArchitectTM and BSDArchitectTM tool suites for memory BIST and boundary scan, respectively. By leveraging the Full-SpeedTM capabilities within the MBISTArchitect tool, this collaboration between industry leading technologies in DFT and embedded memory demonstrates an effective method for reducing test costs while maintaining high product quality.
More than an interoperability effort, MoSys and Mentor have formed this strategic alliance to identify and implement new capabilities within the MBISTArchitect tool to test and qualify embedded memories developed by MoSys. The first results of this effort will be available in early 2002 in the form of additional features to support the various 1T-SRAM interface modes. Additional capabilities to support on-chip memory repair analysis for improved yield will follow.
“Reducing test costs while ensuring product quality has always been a mantra for Mentor Graphics DFT and this alliance with MoSys enables us to achieve these same goals for our mutual customers,” said Lori Watrous-deVersterre, general manager, Design-for-Test, Mentor Graphics. “By incorporating the Full-Speed capabilities of our MBISTArchitect tool, MoSys can continue to provide customers with high quality embedded memories for use in System-on-Chip designs.”
“We are proud to be working with Mentor Graphics on integrating 1T-SRAM embedded memories with Mentor Graphics’ DFT tools,” said Mark-Eric Jones, Vice President and General Manager of Intellectual Property at MoSys, Inc. “By optimizing the memory BIST controller design to support 1T-SRAM memories, Mentor Graphics will be able to reduce the test time, thereby providing cost benefits to our customers in addition to the high density and manufacturability of our technology. The on-going cooperation regarding on-chip repair analysis will further benefit our mutual customers”.
About MoSys, Inc.
Founded in 1991, MoSys (NASDAQ: MOSY), develops, licenses and markets innovative memory technology for semiconductors. MoSys’ patented 1T-SRAM technology offers a combination of high density, low power consumption, high speed and low cost unmatched by other available memory technologies. The single transistor bit cell used in 1T-SRAM technology results in the technology achieving much higher density than traditional four or six transistor SRAMs while using the same standard logic manufacturing processes. 1T-SRAM technology also offers the familiar, refresh-free interface and high performance for random address access cycles associated with traditional SRAMs. In addition, this technology can reduce operating power consumption by a factor of four compared with traditional SRAM technology, contributing to making it an ideal technology for embedding large memories in System on Chip (SoC) designs. 1T-SRAM technology is in volume production both in SoC products at MoSys’ licensees as well as in MoSys’ standalone memories. MoSys is headquartered at 1020 Stewart Drive, Sunnyvale, California 94085. More information is available on MoSys’ website at www.mosys.com