MoSys and Xilinx to Demonstrate Interoperability at DesignCon 2011

SANTA CLARA, Calif., Jan 31, 2011 (BUSINESS WIRE) —

a leading architect of serial chip-to-chip
communications solutions that deliver unparalleled bandwidth performance
for next generation networking systems and advanced system-on-chip (SoC)
designs , today announced that Xilinx, Inc. (NASDAQ: XLNX) has joined
the GigaChip Alliance, an ecosystem of companies that support the
GigaChip Interface. Current alliance participants include: MoSys, Altera
Corporation, NetLogic Microsystems and Xilinx.

In addition, MoSys announced the launch of the GigaChip Alliance
website, which provides information regarding the GigaChip Interface and
the GigaChip Alliance. The Web address is

The GigaChip Interface is a short-reach, low-power serial interface,
which enables highly efficient, high-bandwidth, low-latency performance
not achievable using currently available serial protocols. Similar to
the fundamental performance breakthrough achieved by the move to double
data rate (DDR) style interfaces in the late ’90s, MoSys believes the
GigaChip Interface represents the next breakthrough in chip-to-chip
communications using differential SerDes technology. A 16-lane GigaChip
Interface can replace up to six separate DDR3 parallel interface busses
to memory, which represents a bandwidth density performance increase of
4 times, while reducing system power and interface costs by 2 to 3
times. Such bandwidth density increases will be required to realize line
cards with aggregate throughput beyond 100G, a necessity in future
high-end networking systems. The GigaChip Interface has adopted the open
CEI-11 electrical transport standard, making use of this existing
electrical ecosystem in order to shorten time to market for the
introduction of next generation system designs. Through the GigaChip
Alliance, companies are enabling an entirely new class of low-cost,
high-speed, high-performance systems in networking, computing and
storage markets.

“As the world’s leading provider of programmable solutions, we are
pleased to join the GigaChip Alliance and plan to support the GigaChip
Interface in our FPGAs,” said Sanjay Charagulla, Director, Corporate
Strategic Planning at Xilinx. “We see a major trend towards serial
chip-to-chip communications and believe the GigaChip Interface provides
the efficiency and openness that our customers require.”

“We couldn’t be more pleased to have Xilinx join the GigaChip Alliance
to support the proliferation of the GigaChip Interface into next
generation networking systems,” stated David DeMaria, Vice President of
Business Operations for MoSys. “Our goal is to revolutionize serial
chip-to-chip communications with the GigaChip Interface. Towards that
end, we are making the GigaChip Interface an open protocol and
encouraging widespread use by potential partners and customers. The
GigaChip Alliance will facilitate industry-wide adoption and evolution
of this protocol.”

At the DesignCon 2011 conference being held from January 31 to February
3 at the Santa Clara Convention Center, MoSys and Xilinx will be
demonstrating interoperability between the MoSys Bandwidth Engine(R) IC
and Xilinx FPGAs using the GigaChip Interface. Demonstrations will be
held at MoSys’ booth 516 on February 2 and 3 during the expo portion of
the conference.

About GigaChip Alliance

The GigaChip Alliance is an ecosystem of companies collaborating to
promote and further the development of the GigaChip Interface, a
board-level high-speed serial chip-to-chip communications interface
standard for high-speed networking systems. Developed by MoSys, Inc.,
the GigaChip Interface is an open, CEI-11 compatible high-bandwidth,
low-latency interface for reliable point-to-point communication of
fixed-size frames over short distances. For more information, visit

About Xilinx

Xilinx is the worldwide leader in complete programmable logic solutions.
For more information, visit

About MoSys, Inc.

MoSys, Inc. (NASDAQ: MOSY) is a leading architect of serial chip-to-chip
communications solutions that deliver unparalleled bandwidth performance
for next generation networking systems and advanced system-on-chip (SoC)
designs. MoSys’ Bandwidth Engine family of ICs combines the company’s
patented 1T-SRAM(R) high-density memory technology with its high-speed 10
Gigabits per second (Gbps) SerDes interface (I/O) technology. A key
element of Bandwidth Engine technology is the GigaChip(TM) Interface, an
open, CEI-11 compatible interface developed to enable highly efficient
serial chip-to-chip communications. MoSys’ IP portfolio includes SerDes
IP and DDR3 PHYs that support data rates from 1 – 11 Gbps across a
variety of standards. In addition, MoSys offers its flagship, patented
1T-SRAM and 1T-Flash(R) memory cores, which provide a combination of
high-density, low power consumption, high-speed and low cost advantages
for high-performance networking, computing, storage and
consumer/graphics applications. MoSys IP is production-proven and has
shipped in more than 370 million devices. MoSys is headquartered in
Santa Clara, California. More information is available on MoSys’ website

MoSys, 1T-SRAM and 1T-Flash are registered trademarks of MoSys, Inc. The
MoSys logo, Bandwidth Engine, GigaChip and the GigaChip logo are
trademarks of MoSys, Inc. All other marks mentioned herein are the
intellectual property of their respective owners.

SOURCE: MoSys, Inc.

Shelton Group
Media Contact:
Katie Olivier, 972-239-5119 x128
MoSys, Inc.
Corporate Contact:
Kristine Perham, 408-418-7670