Fourth Generation Memory Compilers Broaden the Reach
of Ultra-Dense Single Transistor SRAM
SUNNYVALE, CA, and FREMONT, CA (January 31, 2000)—
MoSys, Inc. and Virage Logic Corp. have established a partnership
to develop fourth generation memory compilers based on MoSys’ 1T-SRAM
and Virage’s Custom-Touch compiler technologies for TSMC’s 0.18-
and 0.15-micron standard logic processes.
These memory compilers are designed to enable system designers
requiring ultra-dense memory to easily embed large quantities of
cost-effective memory in their designs.
By combining Virage’s industry-leading Custom-Touch compiler technology
with MoSys’ volume production-proven 1T-SRAM memory technology,
customers will have the flexibility of rapidly generating the high-capacity
memory instances of their choice at any stage of the design cycle.
The compilers will facilitate “what-if-analysis” and performance
trade-off decisions early-on in the design cycle.
The Custom-Touch 1T-SRAM compilers will have a template generation
mechanism for EDA (Electronic Design Automation) models that will
empower users to freely choose from one of many popular design flows
and ensure that all the necessary information is automatically generated
for integrating and verifying the memories.
Additionally, Virage’s compiler development process subjects all
released products to rigorous testing as part of the company¹s FirstPass-Siliconä
program. For these compilers, TSMC will manufacture the test chips
and Virage and MoSys will rigorously test and evaluate the Custom-Touch
1T-SRAM compiled instances in silicon. This will provide customers
with a comprehensive silicon report, giving them additional confidence
that their compiled memories will work in silicon.
“TSMC’s deep submicron process give our customers the platform
for their complex SOC products,” said Roger Fisher, TSMC’s
senior director, corporate marketing. “Custom-Touch 1T-SRAM
compilers for our leading 0.15 and 0.18-micron processes gives customers
easy access to high capacity memory required in these designs.”
Availability of the first of these Custom-Touch 1T-SRAM compilers
is scheduled for Q2, 2000.
“We are pleased to make Custom-Touch 1T-SRAM compilers available
to TSMC customers” said Vin Ratford, Virage Logic’s vice president
of marketing and sales. “The MoSys-Virage partnership is committed
to proliferating this unique memory technology to enhance productivity
and enable system designers to make smart technical decisions without
making any unnecessary compromises. For the first time, the performance
benefits of SRAM and density advantages of DRAM can be combined
in a compilable form”.
Memories built using the compiler will include the same yield-enhancing
built-in sector redundancy proven in the volume production of 1T-SRAM
devices. Compiled memory users can now build optimal designs without
having to compromise between density, performance, and power.
“Custom-Touch 1T-SRAM compilers deliver the memory innovation
and ease-of-use that TSMC’s customers have come to expect from MoSys
and Virage”, stated Mark-Eric Jones, vice president and general
manager of intellectual property at MoSys, Inc. “By working
with TSMC to enable both their 0.18-micron and 0.15-micron customers,
our partnership is facilitating the memory integration that is critical
for the broader adoption of SoC methodology.”
Available in densities up to 128Mbits, MoSys’ patented 1T-SRAM
technology uses a single transistor cell to achieve its exceptional
density while maintaining the refresh-free interface and low latency
random memory access cycle time associated with traditional six-transistor
SRAM cells. Embedded 1T-SRAM allows designers to get beyond the
density limits of six-transistor SRAMs; it also reduces much of
the circuit complexity and extra cost associated with using embedded
DRAM. 1T-SRAM memories can be fabricated in either pure logic or
embedded memory processes using as little as one ninth of the area
of traditional six-transistor SRAM cores. In addition to the exceptional
performance and density, this technology offers dramatic power consumption
savings by using under a quarter of the power of traditional SRAM
memories. 1T-SRAM technology is volume production proven in millions
of MoSys’ discrete memory devices.
About Custom-Touch 1T-SRAM Compiler
Custom-Touch 1T-SRAM compiler is a single-port, synchronous, multi-megabit
compiler capable of producing memories in densities ranging from
512 kilobits to 64 megabits and will generate complete, verified
design data and models for the most popular EDA tools. It will be
used for networking, graphics, communications and other applications
requiring large blocks of memory on a chip, in a much smaller die
area than previously possible using traditional SRAM. For applications
requiring it, a built-in-self-test (BIST) option is also available.
The Custom-Touch 1T-SRAM compiled memory will include a volume production-proven
redundancy scheme to optimize the yield for these large memories.
Custom-Touch 1T-SRAM compilers can be purchased from both MoSys
About Virage Logic:
Virage Logic is the technology and market leader in application-specific
embedded memory. The company¹s products include optimized memory
compilers, software tools that enable the development and reuse
of memory, and custom memory design services. Virage’s customers
include the leading semiconductor and electronic systems companies
designing ASIC and system-on-a-chip applications. The memory products
developed by Virage are used by fabless semiconductor companies
targeting pure-play foundries and are also optimized for semiconductor
companies. Founded in January 1996, the company is privately held,
and is located at 46501 Landing Pkwy., Fremont, Calif. 94538. Telephone:
(877) 360-6690 (toll free) or (510) 360-8000. Fax: (510) 360-8099.
For more information, please visit www.viragelogic.com.
TSMC (ADS traded NYSE: TSM, also traded on TSE) is the world’s
largest dedicated integrated circuit (IC) foundry and offers a comprehensive
set of IC fabrication processes, including processes to manufacture
CMOS logic, mixed-mode, volatile and non-volatile memory and BiCMOS
chips. Currently, TSMC operates two six-inch wafer fabs (Fab 1 and
2) and three eight-inch wafer fabs (Fab 3, 4, and 5) all located
in Hsin-Chu, Taiwan.
In mid-1998, TSMC announced that production wafers were being delivered
from its first U.S. foundry, WaferTech, a joint venture with Altera,
Analog Devices and Integrated Silicon Solutions, Inc. The company
has broken ground in the new Tainan Park, which will house Fabs
6 and 7 and recently announced its participation in a $1.2 billion
joint venture fab with Philips Semiconductor which is scheduled
to open in Singapore in 2000. TSMC’s corporate headquarters are
in Taiwan. More information about TSMC is available through the
World Wide Web at http://www.tsmc.com.tw.
MoSys, Inc. is the leading semiconductor technology company specializing
in innovative, high performance, random access memories including
products based on its patented 1T-SRAM technology. Founded in 1991,
the company develops and markets memory integrated circuits as well
as licenses memory technology and cores to semiconductor and systems
companies. The company’s unique memory architecture has been proven
in the volume production of over 30 million memory devices. Licensees
that are adopting 1T-SRAM technology include tier one electronics,
semiconductor and foundry companies. The company is headquartered
at 1020 Stewart Drive, Sunnyvale, California, 94086. More information
on MoSys is available at http://www.mosys.com.
Note for Editors:
Custom Touch is a trademark of Virage Logic Corporation.
1T-SRAM is a trademark of MoSys, Inc. All other trademarks or registered
trademarks are the property of their respective owners.