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Superior Memory Performance

MoSys is recognized as an innovative leader in memory architectures. Our family of Accelerator Engine Memory ICs ushers in a new era of memory performance by combining our 1T-SRAM, 6T-SRAM with In-Memory Function (IMF) technology.

Memory Capacity

The Accelerator Engine Memory IC family includes the Bandwidth Engine 2 (BE-2 Burst, BE-2 Macro), Bandwidth Engine 3 (BE-3 Burst, BE-3 Macro) and Programmable HyperSpeed Engine (PHE) ICs. Their memory capacity and density have continued to increase, with the PHE delivering over 1.3 Gb of memory.

  BE-2BE-3PHE
Part NoBE-620BE-622BE-820BE-630BE-830PSE-S30
Density576Mb576Mb576Mb1.152Gb1.152Gb1.152Gb
Fast 6T-SRAMPartitions8
Banks p/Partition72
Capacity2.3Mb
1T-SRAMPartitions444444
Banks p/Partition64646412812872

Superior, High Speed Random Access Memory Architecture

The heart of the memory IC is our advance, parallel array 1-T SRAM with a capacity of 576Mb.

  • The memory is divided into 4 partitions.  Each partition has 64 banks allowing parallel (simultaneous) access.
  • Since there are two independent I/O ports per device, several memory access as well as multiple EIMFs can be executing at the same time.
  • Can be used as a Dual-Port memory

The tRC is 2.67 ns allowing up to 5 billion transactions per second.

High-Speed Serial Protocol I/O Interface

Our 16 SerDes lanes can transmit data up to 28Gbps, with a optional rates of 10Gbps and 15Gbps.  MoSys' GigaChip Interface (GCI) delivers  full duplex, CRC protected data throughput, enabling up to 10 Billion memory transaction per second on as few as 16 signals.

Traditional memory design requires a lot of interface pins (in some cases 1000’s of pins), making signal routing and integrity a design challenge.

Each Accelerator engine has 2 completely independent, 8 lane, I/O ports that allow simultaneous memory access operations.

Easy to Design-In

  • Fewer pins using serial I/O with the GigaChip Interface technology
  • Clean and reliable signal integrity board layout
  • Standard use as a QDR replacement

Simple to understand EIMF (Embedded In-Memory Functions) to accelerate performance

A lot of high speed random access memory, with easy to understand EIMFs, with so few signal pins.

Cannot get simpler than that!

Fixed In-Memory BURST Functions

The BURST Functions are focused on DATA MOVEMENT where they accelerate getting data in and out of the memory faster and more efficiently by reducing the number of commands.

The BURST Multi-Read/Multi-Write In-Memory Functions can combine up to 8 READS or 8 WRITES into a single BURST function. This reduces the number of memory accesses when moving data, nearly doubling the amount of data that can be moved with that same bandwidth.

And, the Accelerator Engine can do several BURST Functions simultaneously!  Further increasing system performance.

BURST Accelerator Engine IC Architecture Overview

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