Select Page

Bandwidth Engine 2 – BURST Memory IC

The BE2-BURST features a multi-level high-performance SRAM memory with Embedded In-Memory BURST functions for greater data transfer efficiency. We combine this with our high-speed serial protocol I/O interface to accelerate your application’s performance.

BURST Accelerator Engine ICs

Superior, High Speed Random Access Memory Architecture

The heart of the memory IC is our advance, parallel array 1-T SRAM with a capacity of 576Mb.

  • The memory is divided into 4 partitions.  Each partition has 64 banks allowing parallel (simultaneous) access.
  • Since there are two independent I/O ports per device, several memory access as well as multiple EIMFs can be executing at the same time.
  • Can be used as a Dual-Port memory

The tRC is 2.67 ns allowing up to 5 billion transactions per second.

Fixed In-Memory BURST Functions

The BURST Functions are focused on DATA MOVEMENT where they accelerate getting data in and out of the memory faster and more efficiently by reducing the number of commands.

The BURST Multi-Read/Multi-Write In-Memory Functions can combine up to 8 READS or 8 WRITES into a single BURST function. This reduces the number of memory accesses when moving data, nearly doubling the amount of data that can be moved with that same bandwidth.

And, the Accelerator Engine can do several BURST Functions simultaneously!  Further increasing system performance.

The Ideal Replacement for Your Current QDR SRAM

Let’s face it. You love the speed and bandwidth performance of your QDR SRAM, but you don’t like the fact that sometimes you need up to eight of them with the high signal pin count needed to get the performance you’re looking for.  Our multiport, serial, single-transistor SRAM eliminate all of these issues.

You don’t need more ICs, you just need one that is better!

High-Speed Serial Protocol I/O Interface

Our 16 SerDes lanes can transmit data up to 12.5Gbps, with an optional rate of 10Gbps.  MoSys' GigaChip Interface (GCI) delivers  full duplex, CRC protected data throughput, enabling up to 10 Billion memory transaction per second on as few as 16 signals.

Traditional memory design requires a lot of interface pins (in some cases 1000’s of pins), making signal routing and integrity a design challenge.

Each Accelerator engine has 2 completely independent, 8 lane, I/O ports that allow simultaneous memory access operations.

Easy to Design-In

  • Fewer pins using serial I/O with the GigaChip Interface technology
  • Clean and reliable signal integrity board layout
  • Standard use as a QDR replacement

Simple to understand EIMF (Embedded In-Memory Functions) to accelerate performance

A lot of high speed random access memory, with easy to understand EIMFs, with so few signal pins.

Cannot get simpler than that!

Key Specifications

Part Number: MSR620
Total Memory Density: 576Mb
Max tRC: 2.67ns
Transactions: 5 Billion p/s
Package: BGA
Footprint: 19mm x 19mm


HyperSpeed Engine Programmable (HEP-PROG) Performance and Features Snapshot

Density (Mb)

tRC (ns)

BURST Embedded In-Memory Functions for superior bandwidth performance.

Max SerDes Rate (Gbps)

Latency (ns)

Buffer BW (Gbps)

Billion Accesses (ps)

Bandwidth Engine 2 – BURST Architecture

Understanding MoSys’ Advanced 1T-SRAM Technology

Parallel Array Architecture

  • 16 outstanding transactions
  • 3.75 Billion Transactions per Second
  • 160Gbps full duplex throughput
  • 16ns deterministic read latency
  • 2.67ns Random Cycle time (tRC)

GigaChip Interface

  • 90% efficient throughput
  • Up to 16 low-latency SerDes lanes (12.5Gbps or 25Gbps)

Single-Cell SRAM 70x better SER

  • Full ECC support
  • CRC protected and self-recovering
  • SEU resistant

BE2-BURST Embedded In-Memory BURST Functions

BURST Fixed-Functions

Burst functions are designed to get data in and out the memory more efficiently by reducing the number of commands. Normal transmission requires one command for each transfer of data. However, by bundling eight packages of data to a single command, you’ve eliminated seven unnecessary commands. You can bundle 2, 4 or 8 data packets.

    SerDes Speed Grade
    WidthBURSTThroughput (Gbps)Throughput (Gbps)Throughput (Gbps)
    16 LanesBL8160200320
    8 LanesBL880100160
    4 LanesBL8405080

    BE2 Embedded In-Memory BURST Function Opcode Map

    Share This