MoSys Use Case Packet Classification in 5G UPF (User Plane Function) Fixing LPM Routing Bottlenecks in New 5G Networks – It’s All About Data Movement

By Julie DiBene

Director, Marketing Communications

Heralded as the next best thing in mobile network technology, 5G has not come without its headaches and challenges. One of the biggest challenges now facing 5G operators lies in creating a quicker, latency sensitive, and cost-effective gateway function between the edge and the data network. This challenge is becoming more and more difficult as mobile network traffic shows no signs of slowing down. In fact, preliminary data from 5G networks already are showing that the typical 5G user equipment is devouring three times more data than its 4G counterpart.

The User Plane Function (UPF) is a critical part of a 5G core infrastructure system architecture. Fundamentally, Control and User Plane Separation (CUPS) works by decoupling Packet Gateway (PGW) control and user plane functions. This, in turn, enables the data forwarding component to be decentralized. This is how packet processing and traffic aggregation moves closer to the network edge which as we know, is one of the most effective ways to increase bandwidth productivity.

Data moving through the 5G network must meet certain time domain response requirements. One of the key bottlenecks is found where data passes from the over the air portion to the wired network. The 5G UPF is the workhorse that connects the actual data coming over the Radio Area Network (RAN) to the Internet. Being able to quickly and accurately route packets to the correct destination on the internet is critical to improving efficiency and customer satisfaction.

Routing in and of itself requires headers of each packet be examined in real-time. Known as Deep Header Inspection (DHI) this function provides searches that can use a combination of Exact Match or Longest Prefix Match (LPM). Depending upon the system, the total number of rules, the number of rules that match, the complexity of the rules and the speed of the searches (Millions of searches per sec) determine the overall performance level.

Nailing demanding search requirements can be achieved in a number of ways, including utilizing a solution in Software although this solution can be too slow to meet current requirements. Another way can be to use a standalone TCAM chip but this is costly and requires a lot of power. Other solutions include using a hardware accelerated Algorithmic TCAM in ASIC or FPGA (Which MoSys provides) or combining a multi-terabit Smart Switch with any of the afore listed. 

This Ultra-High-Speed Search Engine IP and Deep Header Inspection (DHI) solution is available for ASIC or FPGA and optimized for high performance routing. It is ideal for applications like 5G UPF and can easily add other functions. Tuned for Longest Prefix Match (LPM), it can address any mix of IPV4 and IPV6 lookups while being optimized for 1 or 2 tuple matches including support for virtual routes. The solution supports broad range of devices and can utilize hybrid mix of memories. It can also use MoSys memories, but can operate without any MoSys silicon present and supports RTL for Intel Stratix 10, Xilinx UltraScale+ FPGAs, or ASIC/ SoC/DPU. The MoSys solution replaces multiple expensive and power hungry TCAM chips  and is applicable to designs based on NIC, SmartNIC, DPU, Standalone SoC, SmartSwitch and more.

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