Future Proofing Your Next DesignWednesday February 17, 2021
By Mark Baumann
Director, Product Definition & Applications
System throughput and individual interface speeds continue to increase. With this, the burden to support faster accesses of both buffers and tables as well as increasing the storage capability of buffers that can act as a form of shock absorber for systems during times of high traffic, has always been a design concern. The need to run even faster is just exaggerating the issue. Let’s look at an example of a network system that in the past, interfaced to switches and routers at speeds of 40 Gbps and even 100Gbps.
In today’s systems, the individual interface speeds are ranging from 100Gbps to 400Gbps and a system will aggregate multiples of that to switch at speeds of 1Tbps and higher. The drive to have every bit of voice, video, and data flow across the internet is driving the bandwidth and throughput of the link into and out of everyone’s home and business to continually support a greater information throughput. As well as preparing the world for the IoT (Internet of Things) in which an additional myriad of devices will be requesting access to pass data across the internet, albeit small data but huge numbers of items will be sending small packets of information, making the speed at which new packets need to be processed ever increasing.
In our discussions with customers, it is not an uncommon practice to provision ingress and egress hardware to be capable of compensating for high traffic scenarios by allocating over-subscription buffering that can absorb high bandwidth traffic and allow the processing system time to “catch-up”.
As an example, if we assume that an interface is running at 100Gbps, and the need to provision for a small amount of high traffic, if you were to use a standard QDR device that would allow less than 1.5ms of buffer. If a MoSys device were used in this same application, it would allow for between 6ms to 12ms of buffer time.
If we use an alternate criteria of being able to allocating board space for a single device that can support this application at the bandwidth required to buffer a 100Gbps stream of traffic, with a MoSys device verses other high-speed memories like QDR, the design gains 4x to 8x the buffer time and density of other devices by using a MoSys high-speed memory.
In applications like networking, Data Center switching and load balancing, there are many scenarios in which the data traffic patterns are irregular and experience peaks of much higher-than-average data traffic. These are not constant and, in most instances, not a viable reason to design a system for this level of traffic flow. It tends to be spotty and has somewhat of a predictable pattern. Therefore, a solution that provides a short-term solution to help smooth out the occasional and predictable high traffic times would result in an acceptable option.
To make accommodations for this burstiness of traffic, a device that has high enough bandwidth to support the link speed of the system and enough capacity to provide a system with some meaningful reaction and recovery time is what is ideally needed.
Key System Considerations
Systems on the market have a requirement to meet the promised system throughput, in today’s markets that is ever increasing from 100s of Gbps to Tbps. While providing safe – secure data transfer. To support these requirements, it is necessary for supporting memory products to support 100s of Gbps read and write accesses. In addition, due to the increased interface speeds, the need for greater memory storage density to allow for a similar buffer time coverage is also required. If a 100Gbps link can fill a 144 Mb memory in 1.5ms, then at 200 , it would be less than 1ms. Moreover, at increasing line rates, it continues to diminish and accentuate the need for an even denser storage option(s).
When summarizing the parameters which are desirable, they are:
- Single device (to minimize board space and routing)
- Interface that can absorb data rates in the 100s of Gbps
- Low Latency
- Random Access rates that do not need to be concerned with issues of refresh and tFAW (like DRAMs)
- Reasonable power and cost
MoSys has a clear understanding of the issues that surround the need for, and lack of, a roadmap for high speed, low latency, low cost next generation memory products. To address this concern, MoSys has developed a family of Accelerator Engine products that can both provide a path to denser, faster and comparably lower cost solutions to the need for a next generation memory product.
MoSys has available, today, devices that are 4x to 8x the density of QDR devices, provide greater bandwidth of memory access at a lower price point, to address the present and even future needs of high speed applications.
If you are looking for more technical information or need to discuss your technical challenges with an expert, we are happy to help. Email us and we will arrange to have one of our technical specialists speak with you. You can also sign up for updates. Finally, please follow us on social media so we can keep in touch.