Packet Classification Apps Just Got a Whole Lot Easier to Accelerate and Manage (Again): MoSys’s New Graph Memory Engine™ IP Running on Intel’s Stratix 10 FPGAs with TCAM CompilerTuesday June 9, 2020
By Gus Lignos
Vice President Sales, MoSys
MoSys recently announced the first products in our new Packet Classification SW Platform that will make use of MoSys’ innovative virtual accelerator, the Graph Memory Engine (GME), for performing embedded search and classification of packet headers as an alternative to TCAM functions. The platform will include the GME and software that compiles TCAM images into graphs for GME processing using a common API for scalability. The GME will be provided as a family of implementations ranging from a pure software version for maximum flexibility and capacity, RTL for use in an FPGA for hardware performance, and a maximum performance RTL solution connected to a MoSys Programmable HyperSpeed Engine (PHE) IC with the GME running as FW on the PHE’s 32 embedded RISC cores. The initial FPGA versions of the GME were compatible with Xilinx UltraScale+. MoSys is pleased to announce that our GME solution is now also available on Intel’s Stratix 10 family of FPGAs and, as was the case with the Xilinx version, will utilize a common RTL interface to facilitate platform portability.
Packet classification apps can now run a whole lot faster because the search performance on an FPGA with a MoSys PHE can result in up to 100x performance over software solutions running on host CPUs with DRAM, which are bottlenecked by random accesses of memory. The PHE version provides enough performance to support two 100G ethernet ports. In short, we have now made our trademark acceleration available to an even wider set of environments while enabling software designers to make use of hardware performance without developing firmware or RTL. This same approach can be applied to a wide variety of advanced embedded applications including key value pair databases, networking search functions, machine learning, computation and algorithm acceleration, all of which can run on different hardware platforms.
Target applications include FPGA-based SmartNICs and acceleration cards in a broad range of markets including: 5G edge compute, router, switching, security (Firewall, ACLs, DDoS, IPS and WAF), computational storage, database acceleration, Big Data, aerospace and defense, test and measurement, advanced video, high-performance computing, machine learning and AI, and other data-driven areas.
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