There is a New Type of Memory (EFAM) in Town Part I of 2Tuesday April 7, 2020
By Mark Baumann Director, Product Definition & Applications, MoSys, Inc.
I have been involved with memory companies for much of the last 30 years. It has been interesting to see the evolution of memory from SRAM densities of 2K x 8 at 70ns access time to today’s SRAMs that are approximately 144Mb with access times in the sub 5ns range. It was a running expectation that what would happen with memories (somewhat in alignment with Moores Law) would be that every couple of years, the density would double, and the speed would also increase.
Along the way that seemed to be exactly what happened. It was somewhat formulaic and boring, to the point that the roadmap for memory had the mantra “bigger, wider, faster”. For the designers of the product, it became somewhat monotonous. In fact, I was in a product planning meeting in which the CEO of the company I was working for at the time started the meeting by stating that he was going to fire the person who just stated that our next product should be, “bigger, wider and faster” than the last.
Although there still exists benefit to this mindset, there was and is a need for more. As time and systems have evolved, it is obvious that bottlenecks in system performance is quite often due to the access that processors have to memory. With Internet speeds commonly running at 100Gbps pipes and soon to be 400Gbps pipes, it is getting easier to move VAST quantities of data. The issue now become what to do with all this voluminous data. Especially in this era of malware and security concerns, vast quantities of the data must be physically touched to ensure its integrity. The partial solution to this issue is to provide large storage with high bandwidth access which is exactly where many of the DRAM products have headed.
If we look at technology directions like those taken by HBM (High Bandwidth Memory), they are taking the bigger (by utilizing the through silicon via technology) to support the stacking of large DRAM die to increase the memory density profile, to an extreme by stacking die, up to 8, to get a maximum memory density profile. In addition, to addressing a bandwidth or potential throughput by utilizing silicon line width and spacing rules to provide very dense I/O and packing hundreds up to a few thousand I/Os on the edge of a piece of silicon with the restriction that it only drive a few millimeters of trace on a silicon interposer or EMIB type structure. This can be seen as following the bigger, faster roadmaps that memories have followed for decades now. The underlying issue with HBM is certainly not the innovative approach they have taken to the bigger faster memory roadmap. The main underlying issue is that it is still a DRAM with the inherent access restrictions of latency and refresh that defines DRAM. It works out well for large bulk storage and data storage that does not require frequent and random access.
What MoSys wishes to address is the areas of the system that require fast, low latency random access to memory. This is not addressed by HBM, we believe we are complimentary to HBM.
The following table relates the differences between a DRAM and DRAM-based device vs. the MoSys BE devices. This again is purely based on I/O access and the ability to access data in a truly random fashion. The difference is seen very plainly when performing random accesses into the memory.
- HBM – 900MHz clock, 32B Random Accesses, 256B for Maximum Read Bandwidth Accesses
- BE3– 1.25GHz clock, 9B for Maximum external measured Random Access Rd + Wr Bandwidth
- PHE– 1.25GHz clock, 18B for Maximum internal measured Random Access Rd + Wr Bandwidth
- HBM maximum access bandwidth as reported in HC29.22.530, maximum random-access rate extrapolated
In Part 2 of this blog, we will explore the ins and outs of EFAM (Embedded Function Accelerator Memory).
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