MoSys is seeking a self-motivated hard-working engineer who can work independently. The Product Engineer will initially be responsible for SerDes characterization on MoSys products. This person will interface with design engineering and applications to find out and understand how to prepare and do the characterization across PVT. The person will interface with the test team to implement production screens to guarantee high quality for outgoing products. The person will operate, and program for, lab equipments such as BERT, scopes, SiliconThermal, and VNA to characterize a device in the characterization boards or under system level tests. Future responsibilities may include characterization of and optimization for memory on MoSys products, and the automation thereof.
Responsibilities
Develop an automatic characterization of SerDes for products
Establish correlation between various platforms and between different loopback modes
Develop screens for production based on:
SerDes characterization of products
Correlation between internal and external loopback in lab, ATE, and MCC
Correlation of System Level test and internal/external loopback
Support design/test of SerDes related PCB boards such as Newton/Edison
Requirements
BS in Electrical Engineering, Computer Science, or equivalent
5+ years of experience in device or SerDes characterization and test
Practical knowledge in the details of high-speed product characterization is a plus
Hands-on experience in the operation of and programming for test equipments such as Oscilloscopes, BERTs, Network Analyzers, Spectrum Analyzers etc. is a plus
Strong skills in debugging, problem solving, and trouble shooting
Ability to set up bench test equipment and build test environments
Good programming skill (preferably Python, TCL, or Perl) are required; GUI programming experience is a plus
Systematic analysis of data, and consistent reporting thereof
The Firmware/Software engineer will be responsible for developing firmware and software package for driving FPGA-based silicon validating system for MoSys Serdes and Memory products. He/She will work with application groups to develop and maintain codes ranging from low-level drivers to high level GUI for customer demo boards and system applications. This person will also develop a flow-based GUI for in-house tester to achieve maximum engineering and manufacturing efficiency.
Responsibilities
Develop serial communication drivers for USB to SPI, I2C, JTAG and MDIO.
Develop GUI on Linux/Windows for customers to evaluate MoSys Serdes/Memory products.
Create GUI to execute flow based test software to facilitate silicon bring up and data collection.
Create a software platform to bridge the gap between pre-silicon verification and post-silicon validation.
Create C compiler to support internal and external customers to program MoSys next generation Bandwidth Engine products.
Develop/maintain software for lab instrument automation and test hardware control.
Requirements
MSEE with 2 years or BSEE with 4 years of related work experience.
Proven skills in C/C++ programming and familiar with object-oriented programming methodology.
Demonstrated GUI design experiences.
Familiar with assembly language is desired. Familiar with Lex and Yacc (Flex and Bison) is a plus.
Familiar with Python. Knowledge of other scripting languages is a plus.
Understand SPI, I2C, JTAG, GPIB and MDIO protocol and low level drivers.
Knowledge of hardware, digital design and design verification is desired.
Experience with FPGA and Xilinx or Altera design tools is a plus.
This position will be responsible for memory architecture and circuit design for new products.
Will interface with applications and marketing to understand the performance requirements; write the
memory block specification of 100Mb+ on-chip memories, interface with logic and timing verification teams; and implement robust circuits with built-in DFT hooks to enable fast bring up and test in production.
Responsibilities
Design large memories in advanced technologies
Invent
Plan ahead and implement test with Built-in Self-test hooks
Supervise layout
Requirements
BS. in Electrical Engineering
5+ years of experience in high speed circuit design
Understand fundamentals of transistors, capacitors, resistors, and inductors
Experience with repeater optimization and clock trees
Experience with .lib generation, synthesis and Place & Route a plus
Understanding of analog blocks such as regulators and charge pumps
Basic programming skills (preferably Python or Perl) for design optimization and verification
This candidate will automate, develop, deply, support and own CAD and integration tools and flows that enhance the efficiency and productivity of the MoSys design teams. The candidate will work/communicate directly with multiple foundry PDKs for leading edge processes. This candidate should be able to develop, deploy and own in-house solutions for any design issues encountered.
Responsibilities
Support the current tools and flows in place
Develop new solutions as needed
Support EM/IR solutions at MoSys
Support CircuitERC
Support Cadence/DM solutions
Requirements
BSEE or MSEE with an electrical or computer background
5-8 years of experience in design automation / CAD
Hands-on experience with Cadence tools (Virtuoso/Composer/Layout)
Experience with version control/config management and release methodologies
Strong coding experience on PERL, TCL and SKILL languages
Hands-on experience in EM/IR tools at the custom and ASIC level
Expertise in functional verification for the ASIC flow
Expertise in development in verification plan, verification environment setup, test bench coding, verification and debug
Hands-on experience in development of chip level and/or block level test-bench environment using System Verilog, Verilog or Specman or Vera
Should encompass Code and functional coverage, equivalence checks, OFT verification and gate level verification
Prior ASIC/FPGA experience is must with sound ASIC flow methodology knowledge, and involved in consumer ASIC I SoC designs
Knowledge about the subset of the VLSI design cycle like behavioral modeling of Bus Functional Models (BFMs), Monitors/Checkers coding, synthesis, timing, OFT, Silicon Validation
This position is on the Bandwidth Engine design team. The Bandwidth Engine products from MoSys, Inc. are memory dominated devices with ALUs and low-latency, high-bandwidth SerDes interfaces. This family of ICs is optimized for high-bandwidth, high-access-rate applications such as networking, storage and video.
Responsibilities
This person will work on the logic design of the Bandwidth Engine SoC. He/She will develop and implement microarchitectures of various features on the next generation high-speed serial memory chip. Excellent logic design skills and experience with developing RTL that meets functionality, timing and power constraints is needed. Background in processor logic design or complex ASICs is required, with excellent knowledge of Verilog and synthesis tools.
Requirements
BS or MS in EE and 5 years of relevant industry experience
Excellent experience with development and implementation of complex microarchitecures and RTL design.
Experience in Verilog and PERL
Experience in synthesis tools like Design Compiler
Excellent team player, innovative and self-driven with good communication skills including documentation.
The Analog Layout Engineer will work on design for SerDes which works at 25Gbps and above in next generation MoSys product series. The team provides a complete solution for various activities like layout issues on 28nm, 45nm & 65nm techology nodes and support to reach the next level with high confidence.
Responsibilities
Analog layout from block level to Chip level.
Strong communication in between various design teams to ensure strong understanding of circuit requirements of layout.
Requirements
BE/Btech/ME/Mtech
Good Knowledge in basics characteristics of electronic components such as transistor, resistor, capacitor, diode and bipolar.
Good understanding of fabrication process.
Familiar with layout techniques and issues in 28nm, 45nm & 65nm Technology nodes.
Understanding of layout impact on device matching, noise coupling, deep sub micron effects.
Understand the importance of signal flow, Clock Routing, Shielding, Load Cap reduction techniques, power & ground structure, Bias signal routing.
Should have good debugging skills in all physical verification checks like LVS,DRC,DFM and Antenna.
Good knowledge on EMIR analysis and ESD path checks.
Thorough working knowledge in physical design and verification tools - Cadence tools (Virtuoso-L,Virtuoso-XL and Schematic composer), Mentor Graphics Calibre and Apache EMIR Analysis.
Knowledge of scripting languages such as Perl and Skill is a plus.
Good verbal/written communication skills with local and remote teams
As a senior DFT engineer, you will be responsible for the architecture and design implementation of
DFT features in MoSys Bandwidth Engine ICs and High-Speed Serdes ICs. You will deliver cutting edge
test solutions to production.
Responsibilities
Design, implementation, and verification of AC/DC scan, JTAG, memory BIST.
Pre-silicon verification including gate level simulation.
Scan compression and ATPG.
Fault modeling and test coverage analysis.
Post silicon validation in both lab and ATE environments.
Requirements
MSEE with 3 years or BSEE with 5 years of related work experience.
Experience with scan insertion, synthesis and timing closure.
Hands-on experience with Synopsys DFTMax/TetraMax tool (TestKompress is a plus).
Comfortable with gate level simulation and debug.
Ability to perform fault/test coverage analysis and improvement.
Experience with post silicon validation. Ability of ATE debug is a plus.
Skills in at least one scripting language (TCL, Perl or Python) are desired.
The P&R engineer will be responsible for physical design of logic blocks utilized in MoSys’ Bandwidth Engine products. The job requires hands-on technical contribution to P&R as well as participation in methodology and design analysis activities. Participation in frequent communication between local physical design team and logic and physical designers in the US will also be expected.
Responsibilities
Floor planning and Place and Route at block level and chip level
Custom Clock Tree / Clock Tree Synthesis (CTS) methodology development
Integration of Custom and ASIC blocks
Active participation in STA by identifying and executing timing ECO’s
Execute tape out sign off checks (LVS, DRC, EMIR, DFM, Signal-EM)
Requirements
BS/Btech/MS/Mtech
Expert user of Synopsys ICC tool- Floor-Planning, Place & Route and Clock Tree Synthesis
Experience in multimillion gate designs on 45nm and 28nm technology full chip (flip chip) designs
Strong debugging skills including STA, CTS and Physical verification
Good experience with Signal Integrity and Crosstalk analysis tools
Good at scripting in TCL, PERL etc
Custom layout design
Circuit design
Logic Synthesis
DFT
Good verbal/written communication skills with local and remote teams
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